udaymach
Newbie level 2
Hi Fnz,
My project is to design a Barrel processor (architecture design and coding in VHDL) in which the architecture doesn't involve any pipelining. I am new to this field and i am not able to find the architecture of this processor anywhere in the internet. Can anyone please help me out................................................ I have given a short note on my project below.
The processor has to execute one instruction from each thread at a time for all threads upto N threads. I need to design the architecture for the Barrel processor and has to implement the processor on a FPGA by using VHDL.
So, I have to take a basic architecture of any of the processor and have to modify it such that the processor has N - number of PC,SP,SR,Thread IDs,etc. for each thread. I have to cycle all these registers of each thread at their turn executing only one instruction at a time.
For example Thread -1 is taken and all its corresponding CPU registers are loaded, then one instruction from this thread is executed. Then again Thread -2 is taken and all its CPU registers are loaded, then one instruction from this thread is executed, etc. upto N threads and again its cycled from the first.
Example:
Thread -1 ACC Ro-Rn PC SP Thread ID Flags Thread-status(En/Disable)
Thread -2 ACC Ro-Rn PC SP Thread ID Flags Thread-status(En/Disable)
Thread -3 ACC Ro-Rn PC SP Thread ID Flags Thread-status(En/Disable)
So, I have to design an architecture first and then i have to code in VHDL.
-
Thanks,
UDAY
My project is to design a Barrel processor (architecture design and coding in VHDL) in which the architecture doesn't involve any pipelining. I am new to this field and i am not able to find the architecture of this processor anywhere in the internet. Can anyone please help me out................................................ I have given a short note on my project below.
The processor has to execute one instruction from each thread at a time for all threads upto N threads. I need to design the architecture for the Barrel processor and has to implement the processor on a FPGA by using VHDL.
So, I have to take a basic architecture of any of the processor and have to modify it such that the processor has N - number of PC,SP,SR,Thread IDs,etc. for each thread. I have to cycle all these registers of each thread at their turn executing only one instruction at a time.
For example Thread -1 is taken and all its corresponding CPU registers are loaded, then one instruction from this thread is executed. Then again Thread -2 is taken and all its CPU registers are loaded, then one instruction from this thread is executed, etc. upto N threads and again its cycled from the first.
Example:
Thread -1 ACC Ro-Rn PC SP Thread ID Flags Thread-status(En/Disable)
Thread -2 ACC Ro-Rn PC SP Thread ID Flags Thread-status(En/Disable)
Thread -3 ACC Ro-Rn PC SP Thread ID Flags Thread-status(En/Disable)
So, I have to design an architecture first and then i have to code in VHDL.
-
Thanks,
UDAY