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| module 2-1mux(x,b,a,s);
input a,b,s;
output x;
wire w1,w2,w3;
not(w1,s);
and(w2,w1,a);
and(w3,s,b);
or(x,w2,w3);
endmodule
module 4-1mux(x,data,sel);
input [3:0] data;
input [1:0] sel;
output x;
2-1mux ins1(w1,data[3],data[2],sel[1]);
2-1mux ins2(w2,data[1],data[0],sel[1]);
2-1mux ins3(x,w1,w2,sel[0]);
endmodule
module 8-1mux(x,data,sel);
input [7:0] data;
input [2:0] sel;
output x;
4-1mux ins1(w1,data[7:4],sel[2:1]);
4-1mux ins2(w2,data[3:0],sel[2:1]);
2-1mux ins3(x,w1,w2,sel[0]);
endmodule |