1) if you are planning to do simulation , do you have simulation models for simulator you are using ?
2) compile/assmbler/linker and hex conversion tools to get a hex code with your testcase
3) are u planning to verify processor subsys ?
To design DSP processor , first you should finalize instructionset and pipeline depth , prefetch buffer ?, how many registers etc ... if you are planning to take the same DSP processor then it is fine and you should have the design spec of same processor ?
when you start design for FPGA better you follow RTL coding guide lines ....
I am attaching a pdf for the same .