[SOLVED] need help in debugging the data_out output of synchronous fifo in verilog

[theHermes]

Hi
I have written a code for synchronous fifo and added a testbench as well. I have obtained the results but I am not able to understand the data out signal. I am not able to understand the meaning of the dout waveform.Kindly help me.


`timescale 10ns / 1ns
module fifo2 (wr, rst,clk,rd,din,full, empty,dout);

input wr,rd,clk,rst;
input [7:0] din;
output full,empty;
output [7:0] dout;
integer count,tmp;
reg [7:0]memory[0:15];
reg full, empty;
reg dout;
initial
begin
count=0;
tmp=0;
end


always@ (posedge clk)
begin

if (rst == 1)
begin
dout <= 0;
empty <= 0;
full <= 0;
end

else if (wr == 1)
begin
if(count == 15)
begin
full <= 1;
end
else
begin
full <= 0;
empty <= 0;
memory[count] <= din;
count <= count + 1;
end
end

else if (rd == 1)
begin
if(count == 0)
begin
dout <= 0;
empty <= 1;
end
else if (count == 1)
begin
empty <= 0;
full <= 0;
dout <= memory[0];
count <= count - 1;
end
else
begin
empty <= 0;
full <= 0;
dout <= memory[0];
for (tmp = 0; tmp<15 ; tmp = tmp + 1)
memory[tmp] <= memory[tmp + 1];
count <= count - 1;
end

end
end
endmodule

//testbench
`timescale 10ns / 1ns
module fifo2testbench();
reg clk;
reg rst;
reg wr;
reg rd;
reg [7:0]din;
wire full,empty;
wire [7:0]dout;

integer i;

always #10 clk=~clk;
initial
begin
clk=0;
rst=1;
#100 rst=0;
wr=1;
rd=0;
din[7:0]=8'b10101010;
#20 din[7:0]=8'b11001100;
#20 din[7:0]=8'b11111111;
#20 wr=0;
rd=1;
#80 rd=0;

rst=1;
#100 rst=0;
wr=1;
rd=0;
for(i=0;i<16;i=i+1)
begin
#20 din[7:0]=8'b00000000;
#20 din[7:0]=8'b10101010;
#20 din[7:0]=8'b11001100;
#20 din[7:0]=8'b11111111;
end
#1000 wr=0;
#10 rd=1;


end
fifo2 myfifo(wr, rst,clk,rd,din,full, empty,dout);
initial
begin
#500;
$display ("at time %0d wr = %b rd = %b clk = %b rst = %b din = %b dout = %b", $time, wr, rd, clk, rst, din, dout);
end

initial
begin
$shm_open("fifo2.shm");
$shm_probe("AS");
#1000 $finish;
end
endmodule

 

[dcreddy1980]

You have declared : reg dout;

Where as it should have been : reg [7:0] dout;

Thats why you see undriven value on [7:1] because of wrong declaration.