Need help for Xilinx ISE ver 6.1

I am using Xilinx ISE Ver 6.1
I have written many programms and test bences in it
The programms are running fine and give me RTL Schematics as well
But what abt their test bences. I have written their test bences but how can i check the code of my test bench.


For example this is code

//dataflow and gate with two inputs
module and2 (x1, x2, z1);
input x1, x2;
output z1;
wire x1, x2;
wire z1;
assign z1 = x1 & x2;
endmodule

***********************************
and this test bench

1 //and2 test bench
module and2_tb;
reg x1, x2;
5 wire z1;
//display variables
initial
$monitor ("x1 = %b, x2 = %b, z1 = %b", x1, x2, z1);
10 //apply input vectors
initial
begin
#0 x1 = 1'b0;
x2 = 1'b0;
15
#10 x1 = 1'b0;
x2 = 1'b1;
#10 x1 = 1'b1;
20 x2 = 1'b0;
#10 x1 = 1'b1;
x2 = 1'b1;
25 #10 $stop;
end
//instantiate the module into the test bench
and2 inst1 (
30 .x1(x1),
.x2(x2),
.z1(z1)
);
endmodule
***************************************
how can i check test becnh and see waveforms in Xilinx ISE