You can try to impliment SDRAM controller in one FPGA and make interface to another one, or even something different let's say two fpga connected to one CPLD with SDRAM controller on it.
Sharing one SDRAm between two FPGAS your layout will complicated, and also you will need to have two SDRAM controllers which is resource waste, and somehow to sync those controllers
Hi, Gentlemen!
Does anybody remember VESA?
Study this document **broken link removed**
It will help you to calculate timing parameters for any resolution.