As you didn't state your process, operating voltage, Vb and operating frequency, I used my own parameters:
90nm process, VDD=1.8V , Vb=0.9V . With C2/C1 = 5 you can't achieve a Gain > 15dB , so I had to reduce C1 to 120fF .
So a gain of about 15 dB can be achieved between 40 .. 100MHz at a power consumption < 200µW, s. the following PDF:
Vtn = 0.3 V, Vtp = 0.38 V, Kn = 730μA/V2, Kp = 91μA/V2,
Power < 200uW, Mid-band Gain > 15dB, R =100K,
CLoad= 100fF, C2=1pF , C1=200fF. The voltage source (Vin) has an intrinsic impedance of 50 Ω.
1. Calculate the aspect ratio of both M1 and M2., such that DC output voltage is midrail
± 10 % .
how to find Vb in such conditions?
I think it will be an iterative process, as you don't know Vb in the beginning.
Start by equalizing the currents through both transistors, and use the strong inversion equation (which will not be valid for M2, as it will show up). Use Vb=0.9V as a first approximation, so you can calculate the aspect ratio:
Thanks very helpful
one more thing, how to calculate the total noise current at the output , if its dependence
on bias and aspect ratio of both transistors.