micro-engineer
Newbie level 4
I have some Questions on the 1.5 bit stage implementations so i hope some one can answer my following questions i hav attached the architecture and the VTC of the Vresidue
1- I dont know. but shouldn't the Vo = Gain ( Vin-Vdac) or Cs/Cf (Vin-Vdac) where i can ratio them to be equal 2 but i found that Vo = (1+Cs/Cf)Vin - Cs/Cf Vdac
2- here i got unequal code length since my Vin ranges from -Vr to Vr and since my first reference voltage is at -Vr/4 and second Vref is at Vr/4 so i got the middle code length (01) of 0.5LSB and the first and last (00 & 11) respect of about 0.75 LSB thts
3- whts the peak value of the Vresidue in the VTC figure..
thnx
1- I dont know. but shouldn't the Vo = Gain ( Vin-Vdac) or Cs/Cf (Vin-Vdac) where i can ratio them to be equal 2 but i found that Vo = (1+Cs/Cf)Vin - Cs/Cf Vdac
2- here i got unequal code length since my Vin ranges from -Vr to Vr and since my first reference voltage is at -Vr/4 and second Vref is at Vr/4 so i got the middle code length (01) of 0.5LSB and the first and last (00 & 11) respect of about 0.75 LSB thts
3- whts the peak value of the Vresidue in the VTC figure..
thnx