Need equivalent code VHDL testbench for Verilog testbench

It has reading external file and applying different values. Need code in VHDL pls help out.... It work fine in modelsim 6.5.

module Buf_tb;

// Inputs
reg clk;
reg reset;

reg [15:0]K_ldpc;

reg [0:0]input1;

integer file;

// Outputs

wire [0:0]output1;

// Instantiate the Unit Under Test (UUT)

Buffer_parity_gen uut (
.clk(clk),
.reset(reset),

.K_ldpc(K_ldpc),

.input1(input1),
.output1(output1)
);

initial begin
clk = 1;
file = $fopen("Input.txt", "r");

forever #50 clk=~clk;

end

initial begin
reset = 1;
#40 reset = 0;
end



always@(posedge clk)
if (reset==0)
begin
$fscanf(file,"%b",input1);
end

initial begin

K_ldpc=16'd32400;

end

endmodule

As a VHDL beginner, Instead of getting someone else to do it for you, why not have a go yourself?

Try X_HDL tool to convert Verilog to VHDL