Hi, everybody,
I am seeking cache controller vhdl example,
I hope some good guy can give me hint or
tell me where I can find it.
It is better a standalone module, simple.
i don't think so. Don't know if opencores for example have cache models.
Looks like some guy wrote for some course project. Sorry.
But might prove useful for educational purposes.
Hello there, hope you don't mind if you can send me the VHDL code for cache memory, i have same project to implement as soon as possible. Pls i'd love to hear from you. Stay bless