You can modify for need by adding a signal say "Up_down".
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter is
port
(
clk:in std_logic;
enable:in std_logic;
clear:in std_logic;
count_outut std_logic_vector(15 downto 0)
);
end counter;
architecture n_counter of counter is
signal s_count : std_logic_vector(15 downto 0);
begin
counting: process(clear ,clk)
begin
if(clear='1')then
s_count<= (others=>'0');
elsif(clk'event and clk='1') then
if (enable ='1') then
s_count <= s_count + 1 ;
end if;
end if;
end process;