Need a VHDL code for 16 bit counter with up range and low range

[seemagoyal44]

i want a vhdl code for 16 bit counter with uprange and low rangei.e input are reset,count enable,considering with up range and low range.

 

[anoop12]

Re: vhdl for counter

very confusing question?
state it clearly

 

[tosonal.jain]

Re: vhdl for counter

do you men to say an up/down counter of 16 bit?

 

[nitin_ndg]

Re: vhdl for counter

You can modify for need by adding a signal say "Up_down".

--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counter is
port
(
clk:in std_logic;
enable:in std_logic;
clear:in std_logic;
count_outut std_logic_vector(15 downto 0)
);
end counter;


architecture n_counter of counter is

signal s_count : std_logic_vector(15 downto 0);

begin

counting: process(clear ,clk)
begin

if(clear='1')then
s_count<= (others=>'0');
elsif(clk'event and clk='1') then
if (enable ='1') then
s_count <= s_count + 1 ;
end if;
end if;
end process;

count_out <= s_count;

end n_counter;

 

[straw]

vhdl for counter

yes,nitin_ndg is right ,you only need add up_down signal,and write a sub counter in the code.

 

[nitin_ndg]

Re: vhdl for counter

Plz tellme ......is it ans ur question or not....
may i help u any more...