need a code to design a Full Adder using a Decoder

vhdl code !!!!!

Hello every one

i need your help in VHDL .

actually i need a code to design a Full Adder using a Decoder ..

and thank you for such great forum ...

salam

this is first one
here u don't have to define an OR gate as you can see




library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity or_1 is
port(
a,b,c,d:in std_logic;
cout: out std_logic
);
end entity or_1;

architecture orbe of or_1 is
begin
cout<=( a or b )or( c or d);

end architecture orbe;









library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Decoder is
port
(
Sel : in std_logic_vector(2 downto 0);

y : out std_logic_vector(3 downto 0);

y2 : out std_logic_vector(3 downto 0)

);
end entity Decoder;

architecture Behavioral of Decoder is
begin
y<= "0001" when Sel="000" else
"0010" when Sel="001" else
"0100" when Sel="010" else
"1000" when sel="111" else
"0000";

y2<= "0001" when Sel="100" else
"0010" when Sel="101" else
"0100" when Sel="110" else
"1000" when sel="011" else
"1000" when sel="111" else
"0000";
end architecture Behavioral;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decfull is
port
( a:in std_logic_vector(2 downto 0);

sum,cout: out std_logic);
end entity decfull ;

architecture dfull of decfull is
signal i: std_logic_vector(3 downto 0);
signal j: std_logic_vector(3 downto 0);

component Decoder is
port
(
Sel : in std_logic_vector(2 downto 0);

y : out std_logic_vector(3 downto 0);

y2 : out std_logic_vector(3 downto 0)

);

end component;




component or_1 is
port(
a,b,c,d:in std_logic;
cout: out std_logic
);
end component;


begin
l1: Decoder port map (a,i,j);
l2r_1 port map ( i(0),i(1),i(2),i(3),sum );
l3: or_1 port map ( j(0),j(1),j(2),j(3),cout);

end architecture dfull ;

Added after 1 minutes:

another one ::

library ieee;
use ieee.std_logic_1164.all;
entity dec is
port(I:in std_logic_vector(2 downto 0);
out std_logic_vector(7 downto 0));
end dec;

architecture d1 of dec is
begin
process(I)
begin
case(I)is
when"000"=>o<="00000001";
when"001"=>o<="00000010";
when"010"=>o<="00000100";
when"011"=>o<="00001000";
when"100"=>o<="00010000";
when"101"=>o<="00100000";
when"110"=>o<="01000000";
when"111"=>o<="10000000";

end case;
end process;
end d1;

library ieee;
use ieee.std_logic_1164.all;
entity ada is
port(a,b,cin:in std_logic;
sum,coutut std_logic);
end ada;

architecture add1 of ada is
signal s:std_logic_vector(7 downto 0);
signal p:std_logic_vector(2 downto 0);


component dec is
port(I:in std_logic_vector(2 downto 0);
out std_logic_vector(7 downto 0));
end component;

begin
p(0)<= a
p(1)<= b
p(2)<= cin

l1:dec port map (p,s);
sum<=(not s(0) or s(1) or s(2) or s(3) or not s(4) or not s(5) or not s(6) or s(7));
cout<=(s(3) or s(5) or s(6) or s(7));
end add1;