Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

NCSU_FreePDK45: The usage of non-SKILL Pcells in Virtuoso is not a supported feature

Status
Not open for further replies.
Y

Yikun

Newbie level 5
Joined
Aug 19, 2013
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
70
I have installed NCSU FreePDK45 design kit for Cadence IC615 but have problem instantiating device layout with the following warning.
*WARNING* (DB-220704): The Pcell super master: NCSU_TechLib_FreePDK45/nmos_vtl/layout is not a SKILL super master. The usage of non-SKILL Pcells in Virtuoso is not a supported feature.

I can only see a white box with cross of the device instance in layout but when I open the layout view of the device itself, it is visible with correct metal layers.

I followed the Setup Files section of the following link to install the kit with correct paths:
https://www.eda.ncsu.edu/wiki/FreePDK45:Manual
and for P-Cells I have installed 64-bit PyCell Studio from Synopsys using instructions from the following link:
https://www.eda.ncsu.edu/wiki/FreePDK45:Using_P-Cells
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top