NC verilog simulation error

eng_ahmed_osama · Jun 6, 2014

I am new in using ncvlog

I have an error when i am trying to simulate simple inverter
It is a schematic running nc-verilog with virtuoso .

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ncelab: *E,CUVMUR (./ihnl/cds0/netlist,19|10): instance 'test.top@Inv_1<module>.PM0' of design unit 'pmos1v' is unresolved in 'worklib.Inv_1:verilog'.
nmos1v NM1 ( .D(Vout), .B(cds_globals.gnd_), .G(Vin),
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ncelab: *E,CUVMUR (./ihnl/cds0/netlist,21|10): instance 'test.top@Inv_1<module>.NM1' of design unit 'nmos1v' is unresolved in 'worklib.Inv_1:verilog'.
ncxlmode: *E,ELBERR: Error during elaboration (status 1), exiting.

my pdk which is GPDK45n

Any help please .

rahul.achates · Jun 18, 2014

whatever design unit is unresolved means there is no module definition. you need to add those module during compilation.

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you can just grep "grep "module pmos1v" " , I believe you will not find anything in database, if you find it then provide that file to the tool.

eng_ahmed_osama · Jun 22, 2014

the pmos1v is library based cell , its a transistor where i can find its verilog represntation

NC verilog simulation error

eng_ahmed_osama

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rahul.achates

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eng_ahmed_osama

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NC verilog simulation error

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