NBTI influence (AgeMOS model for reliability simulation)

[Jeekoky]

Does anyone know TSMC or others has AgeMOS model for their technologies?

i want to do some reliability simulation using Cadence RelXpert. The technology is prefered to be TSMC 65nm. The problem is that i need the AgeMOS model for the simulation. I don't know if the AgeMOS model has been included in TSMC pdk library or i need to get from other place.

Any information?

 

[dick_freebird]

AgeMOS model for reliability simulation

As someone who's spent 20-some years in the high reliability
business, designing to an "aging model" gives me the creeps.
Being as device aging comes down to processing received,
flukes and fate, as much as any explicit process design.

Back in the day, we couldn'trelease a process unless its
drifts were too low to be worth modeling. I guess things are
more sophisticated now. Though I would not call that "better".

Question is, does it have to last until after Christmas, or until
after Neptune.

 

[Jeekoky]

AgeMOS model for reliability simulation

Do you means it makes no sense to have AgeMOS model?

Now i'm involved in a project which want to inprove the analog front end circuit reliability through periodic tuning. I need to varify if the idea is work or not. That is why i need reliability simulation. It quite strange that Cadence provide a very good reliability tools--RelXpert but no AgeMOS model availiable for the common technology.

 

[dick_freebird]

AgeMOS model for reliability simulation

If you have to use a process that has significant aging
effects (I refuse), -and- you can get both quality models /
data for fitting, and certainty that the aging behavior is any
kind of consistent, then modeling what you have to use is
about the only thing you can do.

But in my experience, such as it is, consistency (lack of)
is the real reliability problem.

I'm sure periodic retuning will work, at least until drifts are
beyond the trim range. Seems like merely an extension
of autozero methods, more sparse. But you have to question
whether your drifts will really be confined to the analog
front end, or so pervasive that trimming the front end alone
will not make the larger circuit that much longer-lived.

 

[Jeekoky]

AgeMOS model for reliability simulation

Hi dick_freebird,

After one month work, i have to say you are correct in some points.

I first get the NBTI parameters of TSMC 65nm LP technology. And then generate the model files required by Cadence RelXpert. A folded cascode op-amp with gain boosting was designed as a target.

I simulated the gain of fresh op-amp and then use RelXpert to simulate after stressing under 125 centi-grade temperature for 15 years.

Finnally i found after stress for 15 years, most of the PMOS Vth increase about 1~3%. Yet the DC gain of the op-amp just change about 0.03dB (From 65.94dB to 65.97 dB).

It's depend a lot on the circuit structure and applications!

--Jeekoky

Added after 7 minutes:

Or maybe the NBTI and such reliability things are not issues in 65nm and older technologies.

 

[erikl]

Re: AgeMOS model for reliability simulation

... maybe the NBTI and such reliability things are not issues in 65nm and older technologies.

Of course NBTI is an issue at sub(tenth)micron processes, otherwise the fabs wouldn't use on-wafer NBTI test structures (for temperature accelerated test @ ≈ 500°C).

It's surely not an issue at max. operating temperatures of 125°C, however for automotive max. environmental temp. of 175°C + 25..50 K self-heating, it could.

 

[cybjut]

Does anyone know TSMC or others has AgeMOS model for their technologies?

i want to do some reliability simulation using Cadence RelXpert. The technology is prefered to be TSMC 65nm. The problem is that i need the AgeMOS model for the simulation. I don't know if the AgeMOS model has been included in TSMC pdk library or i need to get from other place.

Any information?

hi，jeekoky,how do you get the NBTI parameters? From foudry or exracting by your self? thanks.