nanavaras6284
Member level 1
I am a student, working on Digital IC design. When I used Nanosim for Post-Layout simulation, it generates a lot of state comparison errors.
The inputs to Nanosim are
1. hspiceD netlist generated from Cadence Virtuoso extracted view from Layout.
2. Vector file generated from VCD file (obtained by NCVerilog simulation of the verilog gate-level netlist and the SDF file generated by SOC Encounter).
3. Configuration file.
The Virtuoso extracted view and Encounter gate-level netlist are checked for LVS and found to be the same.
Why does this State-comparison error occur, when the input files are the same. How should I go about to solve this error?
The inputs to Nanosim are
1. hspiceD netlist generated from Cadence Virtuoso extracted view from Layout.
2. Vector file generated from VCD file (obtained by NCVerilog simulation of the verilog gate-level netlist and the SDF file generated by SOC Encounter).
3. Configuration file.
The Virtuoso extracted view and Encounter gate-level netlist are checked for LVS and found to be the same.
Why does this State-comparison error occur, when the input files are the same. How should I go about to solve this error?