Nanosecond Monostable using ECL Flip Flop D

[gianbo85]

Hi,

I have a PECL trigger signal at a frequency of 40Mhz and pulse width that can be as low as 1-2 ns and I need to adjust the lenght of the pulses using a monostable to 5-10 ns.

Since the pulses are very fast and the rest of the logic on my circuit is PECL I thought about using some monostable circuit with ECL logic. I found googling around that a flip flop D can be used with a delay line to make a monostable but I couldn't find how.

On Semiconductor has some very fast Flip Flops like MC100EP35 or even NBSG53A that can be used...

Any help is appreciated

Have a nice day

Gianluca

 

[FvM]

I expect, that you would make the FF output self-reset the device through the delay line. It's worth a try.

 

[gianbo85]

Thanks,

I had a similar idea, the configuration would be:

-D input always high

-pulsed input connected to CLK

-output delayed and connected to the RESET pin

My only doubt is about the reset part: On Semi datasheets say that the reset is an "Asynchronous Reset" and sets the level of the output LOW when reset is HIGH (see Truth Table on page 2: https://www.onsemi.com/pub_link/Collateral/MC10EP51-D.PDF). Now, if the reset pin is held HIGH by the delayed pulse for 2 ns and then goes LOW, does the output go HIGH again or it remains LOW till the next CLK edge?

Any idea?

Gianluca

 

[FvM]

does the output go HIGH again

Why should it?