optimized
Newbie level 4
- Joined
- Sep 18, 2012
- Messages
- 6
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1,281
- Location
- Egypt
- Activity points
- 1,316
SA,
when I perform an stb analysis in cadence for PLL model I have made using verilog-a i get (nan ) in all the fields of stability
I am putting the Iprobe between the VCO block & the divider block & I am selecting it as a probe of instance
I am sure there is some thing wrong but I do not know which is wrong
when I perform an stb analysis in cadence for PLL model I have made using verilog-a i get (nan ) in all the fields of stability
I am putting the Iprobe between the VCO block & the divider block & I am selecting it as a probe of instance
I am sure there is some thing wrong but I do not know which is wrong