kamlesh_madheshiya
Newbie level 3
I am developing an application which needs to work between RTL and GATE.
i.e. it uses some information from RTL level and some information from corresponding GATE design. It is obvious that during synthesis, tools (DC, RTLC) do changes the names as well as hierarchy. I am facing problem while matching with these names.
I am applying some default matching rules but that's not sufficient.
Can anyone tell me that is there any information dumped by these tools which can be used for name mapping. I know about V-SDC file.
Also I can use output of formal tools but the problem is formal tools are not run on full chip design because of performance and capacity issue so this is not useful for me.
Please do tell me if you have any idea, information or suggestion about this.
Thanks in Advance.
-Kamlesh
i.e. it uses some information from RTL level and some information from corresponding GATE design. It is obvious that during synthesis, tools (DC, RTLC) do changes the names as well as hierarchy. I am facing problem while matching with these names.
I am applying some default matching rules but that's not sufficient.
Can anyone tell me that is there any information dumped by these tools which can be used for name mapping. I know about V-SDC file.
Also I can use output of formal tools but the problem is formal tools are not run on full chip design because of performance and capacity issue so this is not useful for me.
Please do tell me if you have any idea, information or suggestion about this.
Thanks in Advance.
-Kamlesh