None of the explanations makes sense. You don't turn the transistor on at 1.5 V/ms Vds slope. Cgd related turn on would show in V(U7:G), but there's no significant voltage rise. Initial 20 mV peak is realistic according to Vds slope. Drain current starting at about 30V Vds isn't gate triggered, apparently Vds breakdown.
My assumption: defective model. I don't have a recent PSPICE version with BSC320N20 model. Please post netlist (generated .cir file) and transistor model file.