#### Wild Life

##### Member level 1

Code:

```
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity dist_mem_64x8 is
port (
clk : in STD_LOGIC := 'X';
a : in STD_LOGIC_VECTOR ( 5 downto 0 );
qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end dist_mem_64x8;
architecture STRUCTURE of dist_mem_64x8 is
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NlwRenamedSignal_qspo : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
a_2(5) <= a(5);
a_2(4) <= a(4);
a_2(3) <= a(3);
a_2(2) <= a(2);
a_2(1) <= a(1);
a_2(0) <= a(0);
qspo(7) <= NlwRenamedSignal_qspo(0);
qspo(6) <= NlwRenamedSignal_qspo(0);
qspo(5) <= NlwRenamedSignal_qspo(0);
qspo(4) <= NlwRenamedSignal_qspo(0);
qspo(3) <= NlwRenamedSignal_qspo(0);
qspo(2) <= NlwRenamedSignal_qspo(0);
qspo(1) <= NlwRenamedSignal_qspo(0);
qspo(0) <= NlwRenamedSignal_qspo(0);
VCC_0 : VCC
port map (
P => N1
);
GND_1 : GND
port map (
G => N0
);
BU2_XST_GND : GND
port map (
G => NlwRenamedSignal_qspo(0)
);
end STRUCTURE;
```

So, I didn't understood at all what this component is meant to do!

There's a 6 bit input saved in a 6 bit array in an asynchronous mode.

There's an 8 bit out that only gets an one bit signal [NlwRenamedSignal_qspo] for every bit [7 downto 0] of his output

There's an obscure component named BU2_XST_GND

There are two internal signals that seems to be unused [N0 and N1]

So, I didn't understand, what is this code supposed to do? and how could I simply write the 12.4 VHDL code counterpart?

Thanks a lot!