My output is showing high impedence after doing the following please explain

[sam33r]

Hi all,

I am connecting a wire output of a test bench to a module instantiated in a top module. I am defining an input to a top module where this output wire of the test bench is connected. I am getting the correct required value at the module inside the top module, But the output wire of the test bench is shown high impedance in the waveforms. Can any one tell me the reason behind this?

---------- Post added at 06:22 ---------- Previous post was at 06:20 ----------

One more doubt can we define a wire and a port name (wire connected to it) with a same name? will it create problem?

 

[vivek_p]

Did you properly drive the output wire of the test bench?

 

[sam33r]

Yes I guess. The moment I connect this wire with the module port its goes to high impedance state, otherwise it shows the prefect value. Can you explain what does proper driving of output wire means? Thanks

 

[vivek_p]

Can you pls attach ur design and testbench code if possible