devas said:
Hi,
You did not write VHDL code but Verilog code.
A verilog module looks normally:
module <module name>(<i/os>);
<assignments>
endmodule;
As line 25 is an assignment, you must move it to line 28 (behind ");").
Finally an assignment line ends with a semicolon ";" instead of comma.
Success, Devas
now i got this error:
Using target part "3s500efg320-4".
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc3s500e' is a WebPack part.
INFO:Security:61 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:63 - The LM_LICENSE_FILE environment variable is not set.
INFO:Security:68 - Please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
ERROR:Security:7 - A feature for ISE was found but is for the wrong hostid.
ERROR:Security:9 - No 'ISE' nor 'WebPack' feature was available for part
'xc3s500e'.
----------------------------------------------------------------------
No such feature exists.
Feature: WebPack
License path:
C:/.Xilinx\webpack_adds.lic;C:/.Xilinx\xilinx11suite.lic;E:\Xilinx\11.1\ISE/data
\*.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\can_v1_flexlm.lic;E:\Xilinx\11.1
\ISE/coregen/core_licenses\can_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_lic
enses\cpri_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\ethernet_stati
stics_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\ethernet_statistics
_v3_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\eth_avb_endpoint_v1_flex
lm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\fibre_channel_v3_flexlm.lic;E:\X
ilinx\11.1\ISE/coregen/core_licenses\gfp_v1_3_flexlm.lic;E:\Xilinx\11.1\ISE/core
gen/core_licenses\gfp_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\gig
_eth_mac_v8_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\gig_eth_pcs_pma_
v10_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\gig_eth_pcs_pma_v9_flexl
m.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\obsai_v3_flexlm.lic;E:\Xilinx\11.
1\ISE/coregen/core_licenses\pci32_v4_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_
licenses\pci64_v4_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\pcie_blk_p
lus_v1_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\pcie_pipe_v1_flexlm.l
ic;E:\Xilinx\11.1\ISE/coregen/core_licenses\pcix_v6_flexlm.lic;E:\Xilinx\11.1\IS
E/coregen/core_licenses\pci_express_v3_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/cor
e_licenses\pktq_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\pl4_lite_
v4_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\pl4_v8_flexlm.lic;E:\Xili
nx\11.1\ISE/coregen/core_licenses\pl4_v9_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/c
ore_licenses\rio_log_io_v4_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\r
io_log_io_v5_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\spi3_link_v5_fl
exlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\spi3_phy_v5_flexlm.lic;E:\Xili
nx\11.1\ISE/coregen/core_licenses\srio_phy_v4_flexlm.lic;E:\Xilinx\11.1\ISE/core
gen/core_licenses\srio_phy_v5_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_license
s\ten_gig_eth_mac_v8_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\ten_gig
_eth_mac_v9_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\tri_mode_eth_mac
_v3_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\tri_mode_eth_mac_v4_flex
lm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\vlynq_v1_flexlm.lic;E:\Xilinx\11
.1\ISE/coregen/core_licenses\v_ccm_v1_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core
_licenses\v_cfa_v1_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\v_gamma_v
1_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\v_ipipe_v1_flexlm.lic;E:\X
ilinx\11.1\ISE/coregen/core_licenses\v_rgb2ycrcb_v2_flexlm.lic;E:\Xilinx\11.1\IS
E/coregen/core_licenses\v_spc_v1_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_lice
nses\v_ycrcb2rgb_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\xaui_v7_
flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\xaui_v8_flexlm.lic;E:\Xilinx
\11.1\ISE/coregen/core_licenses\Xilinx.lic;E:\Xilinx\11.1\ISE/coregen/core_licen
ses\XilinxFree.lic;e:\Xilinx\11.1\EDK/data/core_licenses\apu_fpu_v2_flexlm.lic;[
...]
FLEXnet Licensing error:-5,357. System Error: 2 ""
For further information, refer to the FLEXnet Licensing documentation,
available at "www.acresso.com".Invalid host.
The hostid of this system does not match the hostid
specified in the license file.
Feature: ISE
Hostid: 00022ae19641
License path:
C:/.Xilinx\webpack_adds.lic;C:/.Xilinx\xilinx11suite.lic;E:\Xilinx\11.1\ISE/data
\*.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\can_v1_flexlm.lic;E:\Xilinx\11.1
\ISE/coregen/core_licenses\can_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_lic
enses\cpri_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\ethernet_stati
stics_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\ethernet_statistics
_v3_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\eth_avb_endpoint_v1_flex
lm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\fibre_channel_v3_flexlm.lic;E:\X
ilinx\11.1\ISE/coregen/core_licenses\gfp_v1_3_flexlm.lic;E:\Xilinx\11.1\ISE/core
gen/core_licenses\gfp_v2_flexlm.l
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
ERROR:Map:258 - A problem was encountered attempting to get the license for this
architecture.
Design Summary
--------------
Number of errors : 1
Number of warnings : 0
Process "Map" failed
Added after 3 minutes:
bigdogguru said:
There are a couple of characters out of place, try this:
Code:
module mysource_xor(in1, in2, out);
// Port Declarations Section
input in1;
input in2;
output out;
//Module Behavior
assign out = in1 ^ in2;
endmodule
My Verilog is a little rusty, but I believe I caught all the syntax errors.
All ports are implicitly declared as
wire.
FYI, Verilog and VHDL are both HDLs, but Verilog is not VHDL.
when i have used this code i got the following message:
Reading design: mysource_xor.prj
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "mysource_xor.v" in library work
Module <mysource_xor> compiled
No errors in compilation
Analysis of file <"mysource_xor.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <mysource_xor> in library <work>.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <mysource_xor>.
Module <mysource_xor> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <mysource_xor>.
Related source file is "mysource_xor.v".
Found 1-bit xor2 for signal <out>.
Unit <mysource_xor> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Xors : 1
1-bit xor2 : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Xors : 1
1-bit xor2 : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <mysource_xor> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block mysource_xor, actual ratio is 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 6.209ns
=========================================================================
Process "Synthesis" completed successfully
Command Line: E:\Xilinx\11.1\ISE\bin\nt\unwrapped\ngdbuild.exe -ise
Test_1_XOR.ise -intstyle ise -dd _ngo -nt timestamp -i -p xc3s500e-fg320-4
mysource_xor.ngc mysource_xor.ngd
Reading NGO file "E:/Xilinx/workspace/Test_1_XOR/mysource_xor.ngc" ...
Gathering constraint information from source properties...
Done.
Resolving constraint associations...
Checking Constraint Associations...
Done...
Checking Partitions ...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Writing NGD file "mysource_xor.ngd" ...
Total REAL time to NGDBUILD completion: 2 sec
Total CPU time to NGDBUILD completion: 2 sec
Writing NGDBUILD log file "mysource_xor.bld"...
NGDBUILD done.
Process "Translate" completed successfully
Using target part "3s500efg320-4".
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc3s500e' is a WebPack part.
INFO:Security:61 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:63 - The LM_LICENSE_FILE environment variable is not set.
INFO:Security:68 - Please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
ERROR:Security:7 - A feature for ISE was found but is for the wrong hostid.
ERROR:Security:9 - No 'ISE' nor 'WebPack' feature was available for part
'xc3s500e'.
----------------------------------------------------------------------
No such feature exists.
Feature: WebPack
License path:
C:/.Xilinx\webpack_adds.lic;C:/.Xilinx\xilinx11suite.lic;E:\Xilinx\11.1\ISE/data
\*.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\can_v1_flexlm.lic;E:\Xilinx\11.1
\ISE/coregen/core_licenses\can_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_lic
enses\cpri_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\ethernet_stati
stics_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\ethernet_statistics
_v3_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\eth_avb_endpoint_v1_flex
lm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\fibre_channel_v3_flexlm.lic;E:\X
ilinx\11.1\ISE/coregen/core_licenses\gfp_v1_3_flexlm.lic;E:\Xilinx\11.1\ISE/core
gen/core_licenses\gfp_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\gig
_eth_mac_v8_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\gig_eth_pcs_pma_
v10_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\gig_eth_pcs_pma_v9_flexl
m.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\obsai_v3_flexlm.lic;E:\Xilinx\11.
1\ISE/coregen/core_licenses\pci32_v4_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_
licenses\pci64_v4_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\pcie_blk_p
lus_v1_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\pcie_pipe_v1_flexlm.l
ic;E:\Xilinx\11.1\ISE/coregen/core_licenses\pcix_v6_flexlm.lic;E:\Xilinx\11.1\IS
E/coregen/core_licenses\pci_express_v3_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/cor
e_licenses\pktq_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\pl4_lite_
v4_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\pl4_v8_flexlm.lic;E:\Xili
nx\11.1\ISE/coregen/core_licenses\pl4_v9_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/c
ore_licenses\rio_log_io_v4_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\r
io_log_io_v5_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\spi3_link_v5_fl
exlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\spi3_phy_v5_flexlm.lic;E:\Xili
nx\11.1\ISE/coregen/core_licenses\srio_phy_v4_flexlm.lic;E:\Xilinx\11.1\ISE/core
gen/core_licenses\srio_phy_v5_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_license
s\ten_gig_eth_mac_v8_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\ten_gig
_eth_mac_v9_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\tri_mode_eth_mac
_v3_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\tri_mode_eth_mac_v4_flex
lm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\vlynq_v1_flexlm.lic;E:\Xilinx\11
.1\ISE/coregen/core_licenses\v_ccm_v1_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core
_licenses\v_cfa_v1_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\v_gamma_v
1_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\v_ipipe_v1_flexlm.lic;E:\X
ilinx\11.1\ISE/coregen/core_licenses\v_rgb2ycrcb_v2_flexlm.lic;E:\Xilinx\11.1\IS
E/coregen/core_licenses\v_spc_v1_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_lice
nses\v_ycrcb2rgb_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\xaui_v7_
flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\xaui_v8_flexlm.lic;E:\Xilinx
\11.1\ISE/coregen/core_licenses\Xilinx.lic;E:\Xilinx\11.1\ISE/coregen/core_licen
ses\XilinxFree.lic;e:\Xilinx\11.1\EDK/data/core_licenses\apu_fpu_v2_flexlm.lic;[
...]
FLEXnet Licensing error:-5,357. System Error: 2 ""
For further information, refer to the FLEXnet Licensing documentation,
available at "www.acresso.com".Invalid host.
The hostid of this system does not match the hostid
specified in the license file.
Feature: ISE
Hostid: 00022ae19641
License path:
C:/.Xilinx\webpack_adds.lic;C:/.Xilinx\xilinx11suite.lic;E:\Xilinx\11.1\ISE/data
\*.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\can_v1_flexlm.lic;E:\Xilinx\11.1
\ISE/coregen/core_licenses\can_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_lic
enses\cpri_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\ethernet_stati
stics_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\ethernet_statistics
_v3_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\eth_avb_endpoint_v1_flex
lm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\fibre_channel_v3_flexlm.lic;E:\X
ilinx\11.1\ISE/coregen/core_licenses\gfp_v1_3_flexlm.lic;E:\Xilinx\11.1\ISE/core
gen/core_licenses\gfp_v2_flexlm.l
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
ERROR:Map:258 - A problem was encountered attempting to get the license for this
architecture.
Design Summary
--------------
Number of errors : 1
Number of warnings : 0
Process "Map" failed
Added after 40 seconds:
help me please