How can timing optimization be possible by using MVT libraries and Resizing of the cells ? and what are other timing optimization techniques being used during synthesis process. Please elaborate ?
MVT libraries contains different set of VT library cells. which will have same feature size, and gate thick ness is varied mainly for leakage power optimization.
synthesis techniques :
generic optimization : logic optimization, boundary optimization, restructuring.
mapped: selecting best candidate cells in the libs. and cell sizing for meeting timing.
incrimapped: timing optimzation