draser
Member level 2
Hello,
I get the following error when i try to simulate a vhdl netlist file(my_design.vhd) with the relative .sdf file .
Anyone knows how can i solve this?
Thank you in advance
I get the following error when i try to simulate a vhdl netlist file(my_design.vhd) with the relative .sdf file .
# ** Fatal: SDF files require Altera primitive library
# Time: 0 ps Iteration: 0 Instance: /counter File: C:/Users/Alex/Desktop/my_design.vhd Line: UNKNOWN
# FATAL ERROR while loading design
# Error loading design
Anyone knows how can i solve this?
Thank you in advance