Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Multisource error during synthesis

Status
Not open for further replies.

karper1986

Member level 2
Joined
Mar 13, 2009
Messages
49
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,715
hi friends,

I have some problem in sinthesis:

///////////////////////////////////////////Have some always statement:

always @(readmem_en or dd_bfp_out_a or dd_bfp_out_b or dest_bank)
begin

if (readmem_en == 0) begin
if (dest_bank == 0 )begin
regbankone[DDDD_RS1] = dd_bfp_out_a; ////////////////////////////////////////////////This is a problem
regbankone[DDDD_RS2] = dd_bfp_out_b; end

if (dest_bank ==1) begin
regbanktwo[DDDD_RS1] = dd_bfp_out_a;
regbanktwo[DDDD_RS2] = dd_bfp_out_b; end
end
end


////////////////////////////////////////////And another always statement:


always @(posedge clk)
begin
if (en_fft==1)
begin
// reset all the signals here
DDDD_RS1<=0;
DDD_RS1<=0;
DD_RS1 <=0;
D_RS1 <=0;

DDDD_RS2<=0;
DDD_RS2<=0;
DD_RS2 <=0;
D_RS2 <=0;

DDDD_input_reg_sel<=0;
DDD_input_reg_sel<=0;
DD_input_reg_sel <=0;
D_input_reg_sel <=0;

DDDD_dest_bank_sel<=0;
DDD_dest_bank_sel<=0;
DD_dest_bank_sel <=0;
D_dest_bank_sel <=0;
end

// DELAY ALL THE SIGNALS HERE //
DDDD_RS1<=DDD_RS1;
DDD_RS1<=DD_RS1;
DD_RS1 <=D_RS1;
D_RS1 <=RS1;

DDDD_RS2<=DDD_RS2;
DDD_RS2<=DD_RS2;
DD_RS2 <=D_RS2;
D_RS2 <=RS2;

dd_bfp_out_a <= d_bfp_out_a;
dd_bfp_out_b <= d_bfp_out_b;
d_bfp_out_a <= bfp_out_a;
d_bfp_out_b <= bfp_out_b;

DDDD_input_reg_sel<= DDD_input_reg_sel;
DDD_input_reg_sel<= DD_input_reg_sel;
DD_input_reg_sel <= D_input_reg_sel;
D_input_reg_sel <= input_reg_sel;

DDDD_dest_bank_sel<=DDD_dest_bank_sel;
DDD_dest_bank_sel<=DD_dest_bank_sel;
DD_dest_bank_sel <=D_dest_bank_sel;
D_dest_bank_sel <=dest_bank_sel;

// Write read data bus onto regbank 1 when reading from memory
if (readmem_en == 1)
begin
regbankone[0] = rd_data0; //////////////////////////////////////////////////////////// // This is a problem
regbankone[1] = rd_data1;
regbankone[2] = rd_data2;
regbankone[3] = rd_data3;
regbankone[4] = rd_data4;
regbankone[5] = rd_data5;
regbankone[6] = rd_data6;
regbankone[7] = rd_data7;
end

end

I know that in sinthesis I cant use the same signals in different statements, but I dont know how to compile them both into one, any suggestions?
Thanks.
 

dcreddy1980

Full Member level 5
Joined
Dec 3, 2004
Messages
243
Helped
46
Reputation
92
Reaction score
21
Trophy points
1,298
Location
Munich, Germany
Activity points
1,532
Looking at u r code, why dont you bring the "readmem_en == 1" condition check to other always block or the safest is to bring the logic in to the current always block(which is flopped). In simple, remove u r combo logic outside, and make it in to single always block which is flopped.

with the above change, you might have to add any pipeline stage for any sselect signal or data signals or so..check it out

you might ask why cant have two always blocks for combo and the other for flop. The reason is simple, if you give me more info i.e. pictures of how your waveform will look like and functionality. we can write logic such a way that you dont have this multisource conflict.


Let me know if you have any questions.

Regards,
dcreddy
 

    karper1986

    Points: 2
    Helpful Answer Positive Rating

karper1986

Member level 2
Joined
Mar 13, 2009
Messages
49
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,715
Hi dcreddy1980,

I`ve tried to do so, but at outputs I`ve different values that I want. Now I dont know how to do it exactly. Maybe, if I sent you the whole code you'll tell me how it must look like.

Best regards,
Karper.
 

dcreddy1980

Full Member level 5
Joined
Dec 3, 2004
Messages
243
Helped
46
Reputation
92
Reaction score
21
Trophy points
1,298
Location
Munich, Germany
Activity points
1,532
yes send me the code and timing diagram, it will be easy to identify how the o/p should look like
 

    karper1986

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top