karper1986
Member level 2
hi friends,
I have some problem in sinthesis:
///////////////////////////////////////////Have some always statement:
always @(readmem_en or dd_bfp_out_a or dd_bfp_out_b or dest_bank)
begin
if (readmem_en == 0) begin
if (dest_bank == 0 )begin
regbankone[DDDD_RS1] = dd_bfp_out_a; ////////////////////////////////////////////////This is a problem
regbankone[DDDD_RS2] = dd_bfp_out_b; end
if (dest_bank ==1) begin
regbanktwo[DDDD_RS1] = dd_bfp_out_a;
regbanktwo[DDDD_RS2] = dd_bfp_out_b; end
end
end
////////////////////////////////////////////And another always statement:
always @(posedge clk)
begin
if (en_fft==1)
begin
// reset all the signals here
DDDD_RS1<=0;
DDD_RS1<=0;
DD_RS1 <=0;
D_RS1 <=0;
DDDD_RS2<=0;
DDD_RS2<=0;
DD_RS2 <=0;
D_RS2 <=0;
DDDD_input_reg_sel<=0;
DDD_input_reg_sel<=0;
DD_input_reg_sel <=0;
D_input_reg_sel <=0;
DDDD_dest_bank_sel<=0;
DDD_dest_bank_sel<=0;
DD_dest_bank_sel <=0;
D_dest_bank_sel <=0;
end
// DELAY ALL THE SIGNALS HERE //
DDDD_RS1<=DDD_RS1;
DDD_RS1<=DD_RS1;
DD_RS1 <=D_RS1;
D_RS1 <=RS1;
DDDD_RS2<=DDD_RS2;
DDD_RS2<=DD_RS2;
DD_RS2 <=D_RS2;
D_RS2 <=RS2;
dd_bfp_out_a <= d_bfp_out_a;
dd_bfp_out_b <= d_bfp_out_b;
d_bfp_out_a <= bfp_out_a;
d_bfp_out_b <= bfp_out_b;
DDDD_input_reg_sel<= DDD_input_reg_sel;
DDD_input_reg_sel<= DD_input_reg_sel;
DD_input_reg_sel <= D_input_reg_sel;
D_input_reg_sel <= input_reg_sel;
DDDD_dest_bank_sel<=DDD_dest_bank_sel;
DDD_dest_bank_sel<=DD_dest_bank_sel;
DD_dest_bank_sel <=D_dest_bank_sel;
D_dest_bank_sel <=dest_bank_sel;
// Write read data bus onto regbank 1 when reading from memory
if (readmem_en == 1)
begin
regbankone[0] = rd_data0; //////////////////////////////////////////////////////////// // This is a problem
regbankone[1] = rd_data1;
regbankone[2] = rd_data2;
regbankone[3] = rd_data3;
regbankone[4] = rd_data4;
regbankone[5] = rd_data5;
regbankone[6] = rd_data6;
regbankone[7] = rd_data7;
end
end
I know that in sinthesis I cant use the same signals in different statements, but I dont know how to compile them both into one, any suggestions?
Thanks.
I have some problem in sinthesis:
///////////////////////////////////////////Have some always statement:
always @(readmem_en or dd_bfp_out_a or dd_bfp_out_b or dest_bank)
begin
if (readmem_en == 0) begin
if (dest_bank == 0 )begin
regbankone[DDDD_RS1] = dd_bfp_out_a; ////////////////////////////////////////////////This is a problem
regbankone[DDDD_RS2] = dd_bfp_out_b; end
if (dest_bank ==1) begin
regbanktwo[DDDD_RS1] = dd_bfp_out_a;
regbanktwo[DDDD_RS2] = dd_bfp_out_b; end
end
end
////////////////////////////////////////////And another always statement:
always @(posedge clk)
begin
if (en_fft==1)
begin
// reset all the signals here
DDDD_RS1<=0;
DDD_RS1<=0;
DD_RS1 <=0;
D_RS1 <=0;
DDDD_RS2<=0;
DDD_RS2<=0;
DD_RS2 <=0;
D_RS2 <=0;
DDDD_input_reg_sel<=0;
DDD_input_reg_sel<=0;
DD_input_reg_sel <=0;
D_input_reg_sel <=0;
DDDD_dest_bank_sel<=0;
DDD_dest_bank_sel<=0;
DD_dest_bank_sel <=0;
D_dest_bank_sel <=0;
end
// DELAY ALL THE SIGNALS HERE //
DDDD_RS1<=DDD_RS1;
DDD_RS1<=DD_RS1;
DD_RS1 <=D_RS1;
D_RS1 <=RS1;
DDDD_RS2<=DDD_RS2;
DDD_RS2<=DD_RS2;
DD_RS2 <=D_RS2;
D_RS2 <=RS2;
dd_bfp_out_a <= d_bfp_out_a;
dd_bfp_out_b <= d_bfp_out_b;
d_bfp_out_a <= bfp_out_a;
d_bfp_out_b <= bfp_out_b;
DDDD_input_reg_sel<= DDD_input_reg_sel;
DDD_input_reg_sel<= DD_input_reg_sel;
DD_input_reg_sel <= D_input_reg_sel;
D_input_reg_sel <= input_reg_sel;
DDDD_dest_bank_sel<=DDD_dest_bank_sel;
DDD_dest_bank_sel<=DD_dest_bank_sel;
DD_dest_bank_sel <=D_dest_bank_sel;
D_dest_bank_sel <=dest_bank_sel;
// Write read data bus onto regbank 1 when reading from memory
if (readmem_en == 1)
begin
regbankone[0] = rd_data0; //////////////////////////////////////////////////////////// // This is a problem
regbankone[1] = rd_data1;
regbankone[2] = rd_data2;
regbankone[3] = rd_data3;
regbankone[4] = rd_data4;
regbankone[5] = rd_data5;
regbankone[6] = rd_data6;
regbankone[7] = rd_data7;
end
end
I know that in sinthesis I cant use the same signals in different statements, but I dont know how to compile them both into one, any suggestions?
Thanks.