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multiply accumulate IP in FPGA

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snehalg

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i am using the multiply and accumulate IP core from Xilinx ,the operation it performs is first multiply the two inputs a and b and give prod= a*b then it subtracts the previous output from Prod
s=s-prod
problem: i m not able to see the s(present) output as it is loop back. in chipscope one of my input is 30Mhz (12 bit samples) and other one is a constant 1(12 bit) has anybody used it anywhere, how can we plot the output samples(12 bit).
 

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