Multiplier from IPcore

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emerson_11

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Hello,
I am doing a work on simple fixed point multiplication with two signed 16 bit input (say a & b) in verilog. I have a array of input where a & b has ten 16-bit input respectively. I want to multiply say a1*b1, a2*b2,etc. in parallel and i want to store the results in a register.I have used multiplier from IP core and i have instantiated in my main module. Can anyone guide how to do this in verilog coding part. Can i instantiate the multiplier 10 times in my main module. If so how could I store all these results in a register?
 

Yes you can instantiate the multiplier 10 times, it means you have 10 multipliers..
 

If so how could I store all these results in a register?
Click to expand...

First store the result of each multiplier in separate registers. When all the o/p registers have valid data (mult complete) then put them inside a big register. You decide the order and you can use the concatenation operator {}.
 

Something like this comes to mind...
Code Verilog - [expand]
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reg [15:0] a [0:9];
reg [15:0] b [0:9];
 
wire [10*32-1:0] mult_results;
 
generate genvar i;
  for (i=0; i<10; i=i+1) begin : multipliers
    // using a multiplier core (leaving out everything but the
    // two inputs and the result).
    multiplier  mult_inst (
      .a    (a[i]),
      .b    (b[i]),
      .mout (mult_results[32*i +:32])
    );
    // or using a simple inferrred multiplier
    assign mult_result[32*i +:32] = a[i] * b[i];
  end
endgenerate


I've left out any clocks (registers) but the concept is what I'm showing. The for loop results in a set of parallel multipliers. It is expected the inputs are already parallel and the output is in one large 320-bit wide output.
 
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