multiplier 8*8 bit in verilog

[kas4569]

hi !
i want to design a multiplier 8*8 for 2's complements in verilog. the multiplier must get x[0:7] and y[0:7] as input which are 2's complements numbers and return another 2's complement as output . i must do it with designing half adder and full adder .
help me :-D

 

[TrickyDicky]

Well, post the code you have written and say what problems you're having with it....

 

[kas4569]

well i am new to verilog !
i just know how can i code half adder and full adder .

i want to use above picture but i don't know how it is possible

 

[TrickyDicky]

I assume this is some sort of school example?
You'll have to write the full and half adder blocks. Then instantiate them and connect them all yourself - one of the most basic things of Verilog. Plenty of examples out there...

 

[bravoegg]

just out of curiosity, how do you guys do math in FPGA?
Take multiplication for example, I always invoke IPcore, except when come coefficients are constants then I'd use shift and add.

As to other operations such as cordic...IPcore is my first choice...

 

[vGoodtimes]

It depends on the situation.

For example, most FPGA's have 18x18 signed multiplication units. I will use "a*b" for small/mid-sized applications based on frequency requirements.

Often, there is a need for a more complex calculation done over multiple cycles. When the FPGA has something like a DSP48, I will use a BRAM+FSM+DSP48+DMEM in a VLIW config to perform the calculation. I'll do SW pipelineing as needed.

Division by a constant can usually be done by multiplication by a constant.

 

[TrickyDicky]

just out of curiosity, how do you guys do math in FPGA?
Take multiplication for example, I always invoke IPcore, except when come coefficients are constants then I'd use shift and add.

As to other operations such as cordic...IPcore is my first choice...

Multiplication I almost always do as a * b. It makes for more readable code. At least for Altera (not tried with Xilinx) you can use the register retiming option to allow the fitter to move your pipeline inside the DSP slice, so in RTL you can have a multiplier followed by a shift register and the fitter will usually give you the best timed option. In altera this will work for single 18x18 and even larger multipliers (50x50 +), although I did hit a bug for stratix 4 forcing me to use the ip core.