multiplie-accumulator unit using radix 2 modified booth algorithm

[gstekboy]

parallel multiplier-accumulator unit using radix 2 modified booth algorithm

For my project I choose "parallel multiplier-accumulator unit using radix 2 modified booth algorithm" as my base paper.
I'm planning to program this MAC unit in verilog.
But I have some doubts related to the concepts , I know that some members of edaboard has already coded this in verilog.If you can share me the code it will be helpful.




View attachment 05337888_2.pdf

 

[VPrasanth]

i hope it will help you

module multiplier_booths #(parameter width = 4, no = 3)( 
output reg [(2*width-1):0] product, 
output reg done, 
input [(width-1):0] multiplicand, 
input [(width-1):0] multiplier, 
input      load, 
input clear, 
input clock ); 

reg [(3*width):0] accumulator; 
reg [no-1:0] count; 
reg [width+1:0] check ; 

always@(posedge clock, posedge clear) 
if(clear) 
begin 
accumulator = 0; 
done = 0; 
check = {(width+1){1'b0}}; 
end 
else if(load) 
begin 
check = {1'b0,multiplier,1'b0}; 
count = {no{1'b0}}; 
end 
else 
begin 
case(check[1:0]) 
2'b10 :  accumulator[3*width:width] = accumulator[3*width-1:width] + ~({{width{1'b0}},multiplicand}) + 1'b1; 
2'b01 :  accumulator[3*width:width] = accumulator[3*width-1:width] +   {{width{1'b0}},multiplicand}; 
default: accumulator = accumulator; 
endcase 

if(count == (width)) 
begin	
done = 1'b1; 
product = accumulator[(2*width-1):0]; 
end 

accumulator = {accumulator[3*width],accumulator[3*width:1]};	
check = {1'b0,check[width+1:1]}; 
count = count + 1'b1; 
end 

endmodule

 

[gstekboy]

i hope it will help you

module multiplier_booths #(parameter width = 4, no = 3)( 
output reg [(2*width-1):0] product, 
output reg done, 
input [(width-1):0] multiplicand, 
input [(width-1):0] multiplier, 
input      load, 
input clear, 
input clock ); 

reg [(3*width):0] accumulator; 
reg [no-1:0] count; 
reg [width+1:0] check ; 

always@(posedge clock, posedge clear) 
if(clear) 
begin 
accumulator = 0; 
done = 0; 
check = {(width+1){1'b0}}; 
end 
else if(load) 
begin 
check = {1'b0,multiplier,1'b0}; 
count = {no{1'b0}}; 
end 
else 
begin 
case(check[1:0]) 
2'b10 :  accumulator[3*width:width] = accumulator[3*width-1:width] + ~({{width{1'b0}},multiplicand}) + 1'b1; 
2'b01 :  accumulator[3*width:width] = accumulator[3*width-1:width] +   {{width{1'b0}},multiplicand}; 
default: accumulator = accumulator; 
endcase 

if(count == (width)) 
begin	
done = 1'b1; 
product = accumulator[(2*width-1):0]; 
end 

accumulator = {accumulator[3*width],accumulator[3*width:1]};	
check = {1'b0,check[width+1:1]}; 
count = count + 1'b1; 
end 

endmodule

sorry it is only a part.
can you PM me the remaining codes.
thanks

 

[VPrasanth]

well i can but its your part to write the code as you are solving the paper, whatever i have posted with that you can analyze and evaluate entire code, if you have queries i can solve them

 

[gstekboy]

well i can but its your part to write the code as you are solving the paper, whatever i have posted with that you can analyze and evaluate entire code, if you have queries i can solve them

but the code you posted is for modified booth.
not related to my project

 

[VPrasanth]

please run the code in Xilinx and see, whether it is related to you or Not and also 70% it is related to your projects need to change some modification so you can develop the new one, This project has already done by so many M.Tech Students and i am the one who examined them

 

[gstekboy]

please run the code in Xilinx and see, whether it is related to you or Not and also 70% it is related to your projects need to change some modification so you can develop the new one, This project has already done by so many M.Tech Students and i am the one who examined them

Sorry , it is not for parallel MAC unit.
it is for MAC unit.