I´d say every data in a nowadays computer is stored in a binary format. It´s always 8 binary bits in a byte.My numbers A and B are stored in Reg in Binary format
Half adder? To achieve what?My numbers A and B are stored in Reg in Binary format and output is next fed as input to half adder ?
My numbers A and B are stored in Reg in Binary format and output is next fed as input to half adder ?
@akamino i have not clearly understood your answer , can you please help me by sending algorithm or code
Seems you want to use binary fixed point numbers. But the representation with only 4 fractional bits is rather inaccurate, exact value is 14/16 = 0.875. If you are satisfied with this precision, you should have mentioned earlier.0.9 in binary is 0.1110
Multiplication of Two Fractional Numbers(Decimal Numbers)
I want to multiply two decimal numbers using verilog (synthesizable code)
A = 0.9
B = 0.9
and want to store result which will be input to a adder
is there any logic which computes multiplication of two decimal numbers?
I am of the view that any intuitive exercise should not be misleading but should match actual work in the industry. Otherwise we are not in the right course.Guess it's an excercise problem about number formats and Verilog coding. In so far, Verilog is probably "needed".
Unfortunately the problem specification is unclear respectively incomplete, e.g. not telling if a binary or decimal fixed point format is intended and if an exact or rounded number representation is expected.
While I understand this opinion, I don´t fully agree with it.I am of the view that any intuitive exercise should not be misleading but should match actual work in the industry. Otherwise we are not in the right course.
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