No, you cannot use std_logic_vector for arithmatic with standard VHDL, because it does not represent a number, just a collection of bits. You should use the the signed and unsigned types instead, and yes multiply and division functions exist for these (but I wouldnt use the divide, because there is no option for pipeling which you will need for any decent clock speed).
No, you cannot use std_logic_vector for arithmatic with standard VHDL, because it does not represent a number, just a collection of bits. You should use the the signed and unsigned types instead, and yes multiply and division functions exist for these (but I wouldnt use the divide, because there is no option for pipeling which you will need for any decent clock speed).
Tricky, I think you're quibbling over meaningless details. The OP asked how to multiply and divide std_logic_vectors. In a pure academic sense, okay, std_logic_unsigned is not part of VHDL "standard". In the real world, where we are actually trying make something that works, std_logic_unsigned is universally used and accepted.
Tricky, I think you're quibbling over meaningless details. The OP asked how to multiply and divide std_logic_vectors. In a pure academic sense, okay, std_logic_unsigned is not part of VHDL "standard". In the real world, where we are actually trying make something that works, std_logic_unsigned is universally used and accepted.
But this is the problem with this - it only lets you do unsigned arithmatic - what about if you need signed in the same design? its a bit rubbish if you have to include both std_logic_unsigned/signed packages and constantly say which one you want. The implementation was also not guaranteed across vendors, so you can never be sure if it behaves the same.
hi, TrickyDicky, may I ask what libraries you include when you do unsigned/signed operations?
I have been using the std_logic_unsigned packages forever... 8-O
thanks...
hi, TrickyDicky, may I ask what libraries you include when you do unsigned/signed operations?
I have been using the std_logic_unsigned packages forever... 8-O
thanks...
Assuming the following:
1. 'a' and 'b' are the std_logic_vector signals to be multiplied or divided and that the result is also a std_logic_vector
2. 'a' and 'b' are to be interpreted as 'signed'
3. use work.ieee.numeric_std.all has been added
Multiply:
x <= std_logic_vector(signed(a) * signed(b));
Divide:
Assumption 4: Amount of logic resources used and clock cycle performance is not at all critical
x <= std_logic_vector(signed(a) / signed(b));
If assumption 4 is not valid, then I suggest you Google for lpm_divide