multiplication and division in vhdl

[imbichie]

Is there any way to multiply and divide the std_logic_vector in the VHDL, without using a multiplier block or shifting mechanism.

Here i need to multiply or divide the std_logic_vector both are varying at run time.

Thanks in Advance.

 

[barry]

Well, if you don't want to use a multiplier and you don't want to do any shifting (I can't understand why), then two choices would be:

1) Use a lookup table
2) Perform repetitive additions (for multiply) or subtractions (for divide)

 

[TrickyDicky]

No, you cannot use std_logic_vector for arithmatic with standard VHDL, because it does not represent a number, just a collection of bits. You should use the the signed and unsigned types instead, and yes multiply and division functions exist for these (but I wouldnt use the divide, because there is no option for pipeling which you will need for any decent clock speed).

 

[barry]

No, you cannot use std_logic_vector for arithmatic with standard VHDL, because it does not represent a number, just a collection of bits. You should use the the signed and unsigned types instead, and yes multiply and division functions exist for these (but I wouldnt use the divide, because there is no option for pipeling which you will need for any decent clock speed).

You most certainly CAN use std_logic_vector for arithmetic as long as you include the std_logic_unsigned library.

 

[TrickyDicky]

You most certainly CAN use std_logic_vector for arithmetic as long as you include the std_logic_unsigned library.

No you cannot, because std_logic_unsigned is not part of the VHDL standard.

 

[barry]

Tricky, I think you're quibbling over meaningless details. The OP asked how to multiply and divide std_logic_vectors. In a pure academic sense, okay, std_logic_unsigned is not part of VHDL "standard". In the real world, where we are actually trying make something that works, std_logic_unsigned is universally used and accepted.

 

[TrickyDicky]

Tricky, I think you're quibbling over meaningless details. The OP asked how to multiply and divide std_logic_vectors. In a pure academic sense, okay, std_logic_unsigned is not part of VHDL "standard". In the real world, where we are actually trying make something that works, std_logic_unsigned is universally used and accepted.

But this is the problem with this - it only lets you do unsigned arithmatic - what about if you need signed in the same design? its a bit rubbish if you have to include both std_logic_unsigned/signed packages and constantly say which one you want. The implementation was also not guaranteed across vendors, so you can never be sure if it behaves the same.

 

[naught]

hi, TrickyDicky, may I ask what libraries you include when you do unsigned/signed operations?
I have been using the std_logic_unsigned packages forever... 8-O
thanks...

 

[K-J]

hi, TrickyDicky, may I ask what libraries you include when you do unsigned/signed operations?
I have been using the std_logic_unsigned packages forever... 8-O
thanks...

use work.ieee.numeric_std.all

This has been the released standard for nearly 20 years.

Kevin

- - - Updated - - -

Is there any way to multiply and divide the std_logic_vector in the VHDL, without using a multiplier block or shifting mechanism.

Here i need to multiply or divide the std_logic_vector both are varying at run time.

Thanks in Advance.

Assuming the following:
1. 'a' and 'b' are the std_logic_vector signals to be multiplied or divided and that the result is also a std_logic_vector
2. 'a' and 'b' are to be interpreted as 'signed'
3. use work.ieee.numeric_std.all has been added

Multiply:

x <= std_logic_vector(signed(a) * signed(b));

Divide:
Assumption 4: Amount of logic resources used and clock cycle performance is not at all critical

x <= std_logic_vector(signed(a) / signed(b));

If assumption 4 is not valid, then I suggest you Google for lpm_divide

Kevin Jennings