Multiplexer using D flip flops

[shikharmakkar]

I want to design a multiplexer using d flip flops and some combinational logic. I tried making the circuit but the output depends on the clock, that is how should I remove the previous state dependency when the clock goes low? Should I first convert it into a d latch and then proceed?

 

[KlausST]

Hi,

Multiplexers usually are non clocked.
D-FlipFlops are clocked.

Why do you want to design a multiplexer with D-FlipFlops?

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There are many multiplexers, we don´t know wich one you want to design.
So please give more information, schematic and tell waht you expect, and what is not like you expected.

Klaus

 

[shikharmakkar]

I want to design a 2:1 mux using d flip flops

 

[FvM]

How about a timing diagram?

 

[shikharmakkar]

How about a timing diagram?

It is an interview question and I don't have any timing diagram for it.

 

[andre_luis]

Just a guess, but suppose the OP is referring to some kind of TDM

 

[shikharmakkar]

Just a guess, but suppose the OP is referring to some kind of TDM

maybe but still, wouldn't it have the previous state dependency? how to remove that previous state?

 

[FvM]

You can't remove, just accept it.

DFFs are often used for continuously clocked high speed multiplexers to regenerate the signal timing.

 

[shikharmakkar]

You can't remove, just accept it.

DFFs are often used for continuously clocked high speed multiplexers to regenerate the signal timing.

ok, then can you design it? what i did was i made the output logic of a mux as the output and put a clk and in clear signal, i put the complement of the clock so that when it goes low, the previous state is removed but it is still edge triggered