boku
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Dear all,
I've faced some problems in synthesis and atpg for 2 scan clocks. My situation is:
1. The top includes other non-scanable blocks such as ROM, analog, test mode entering logic.
2. Scan test mode can be entered only after a specific sequences of 3 pins (T1,T2,T3)
3. Two scan clocks with 8 scan chains (one clock with one chain; the other with 7 chains)
What i'm trying to do is focus on the top scannable block (say DGBLK) and passed the synthesis with pre dft.
After getting the final netlist from layout (it had detached the original scan chains and re-connect the 8 scan chains in its own order), I re-do the scan chain synthesis. Only this time I did the synthesis based on top-level in/out definitions (change the DGBLK into TOP with TOP's io ports so I can generate patterns based on actual ports). However, lots of handcrafted work to be done and the final result shows some warning that "pattern rejected due to 3 preclock constraint violations) with 15% coverage merely.
My tool is Synopsys DC-compiler 2006 and its TetraMax.
Can anyone instruct me how i can solve these problems?
Much appreciated.
Boku
I've faced some problems in synthesis and atpg for 2 scan clocks. My situation is:
1. The top includes other non-scanable blocks such as ROM, analog, test mode entering logic.
2. Scan test mode can be entered only after a specific sequences of 3 pins (T1,T2,T3)
3. Two scan clocks with 8 scan chains (one clock with one chain; the other with 7 chains)
What i'm trying to do is focus on the top scannable block (say DGBLK) and passed the synthesis with pre dft.
After getting the final netlist from layout (it had detached the original scan chains and re-connect the 8 scan chains in its own order), I re-do the scan chain synthesis. Only this time I did the synthesis based on top-level in/out definitions (change the DGBLK into TOP with TOP's io ports so I can generate patterns based on actual ports). However, lots of handcrafted work to be done and the final result shows some warning that "pattern rejected due to 3 preclock constraint violations) with 15% coverage merely.
My tool is Synopsys DC-compiler 2006 and its TetraMax.
Can anyone instruct me how i can solve these problems?
Much appreciated.
Boku
