The system is a parallel resonant LC with a coil on the output. The coil changes with the application. Big coil for bigger loads, small coil for smaller load. The inverters output goes to a transformer and then goes to the output coil producing eddy currents which heat the metal in the coil. The system will have a Q-curve associated with it with the peak power corresponding with resonance. Depending on the matching of all the parameters of the system this Q-curve could be either really steep or really flat (ie: low bandwidth or high bandwidth). Where you're operating on this curve is dependent on the switching frequency of MOSFETS on the inverter board. Therefore, if I control the firing frequency then I control where the system is operating on the curve. The bus voltage is fixed I cannot vary it.
The main condition is to not operate past resonance. It is bad for the parts and going above to below resonance on a curve could potentially blow up the components because of going through the peak on the curve.
The problem I'm having with using limits in the PID loops is that they will saturate if another variable is controlling the system because they want to reach their set points, which depending on the system might not be possible to reach. Then, when there is a change to the system these saturated limits don't respond fast enough to take over from the current limit which is heading towards saturation. For example, removing a load from the coil is going to reduce the power but increase the current. If the PID loop output for the current doesn't go below the power PID loop output before it hits it's limit, the system will trip.
---------- Post added at 20:54 ---------- Previous post was at 20:46 ----------
The power, voltage, and current don't fluctuate unless I'm switching at different frequencies often, which with the proper k values doesn't happen. The system can control on power, voltage, and current very well. The only issue is with big changes in the system that result in a high dv/dt or di/dt.
It looks like this roughly:
Code ASM - [expand] |
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| voltage_pid: pid
port map(
clk => sys_clk,
reset => pid_reset,
enable => voltage_enable,
ref_val => voltage_set_point,
act_val => voltage_feedback,
output => voltage_freq_ref
);
power_pid: pid
port map(
clk => sys_clk,
reset => pid_reset,
enable => power_enable,
ref_val => power_set_point,
act_val => power_feedback,
output => power_freq_ref
);
current_pid: pid
port map(
clk => sys_clk,
reset => pid_reset,
enable => current_enable,
ref_val => current_set_point,
act_val => current_feedback,
output => current_freq_ref
);
phase_pid: pid
port map(
clk => sys_clk,
reset => pid_reset,
enable => phase_enable,
ref_val => phase_set_point,
act_val => phase_feedback,
output => phase_freq_ref
);
process(sample_clk) begin
if(rising_edge(sample_clk)) then
if((voltage_freq_ref < current_freq_ref OR voltage_freq_ref = current_freq_ref) AND (voltage_freq_ref < phase_freq_ref) AND (voltage_freq_ref < power_freq_ref OR voltage_freq_ref = power_freq_ref)) then
duty_cycle_ref <= voltage_freq_ref;
elsif((current_freq_ref < voltage_freq_ref AND current_freq_ref < phase_freq_ref) AND (current_freq_ref < power_freq_ref OR current_freq_ref = power_freq_ref)) then
duty_cycle_ref <= current_freq_ref;
elsif(power_freq_ref < voltage_freq_ref AND power_freq_ref < current_freq_ref AND power_freq_ref < phase_freq_ref) then
duty_cycle_ref <= power_freq_ref;
else
duty_cycle_ref <= phase_freq_ref;
end if;
end if;
end process; |