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Multiple input PID loops

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Jun 18, 2010
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Multiple SISO PID loops

I have a system that I'm trying to control using feedback that receives voltage(rms), current(rms), phase, and line input power. Currently, I put all these signals into separate PID loops and then take the smallest value of the outputs. This works fine in the steady state and most step changes. But, on the start-up transients I'm having problems with the speed of the system going between the four values. The output range is about 100-2047. What I see happen in my test case is that on start-up the system hits the phase limit. Being in the phase limit causes a max transfer of power, which over 500us causes the voltage to sky rocket. During this period the output of the voltage pid loop does not go below the phase pid loop output, which is sitting at about 1200. As a result, the voltage hits the shut-off level and turns off the system, instead of running at the voltage limit set point.

I know that playing with the k-values can help this, but then my steady state response gets affected as well, which is bad. I've been thinking about somehow limiting the integral value based on the current lowest output of one of the pid loops. The output is updated at the most once every 1us so I have plenty of time to update the register with a comparison operation before the next valid output. Is there a better way to handle these types of systems where some of the transient responses are radically different than the steady state?
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To make anyone understand what you are doing, you should mention which controlled system or plant is actually controlled by the PID controllers. Furthermore one need to know, if the system has multiple manipulated values, respectively what are the algorithms to combine the multiple PID outputs. Which have primary setpoints and which are slave controllers?

I'm controlling the frequency of the MOSFETS on an inverter, which goes to an LC tank. The current(RMS) limit is for the specs of the MOSFETS. The voltage (RMS) limit is for the limit on the caps on the tank. The phase limit is to prevent the system from operating below resonance. The power limit is the main control although in certain cases voltage or current is. There is no combination of the multiple outputs. It just does a comparison and takes the smaller value. All of the set points are run-time adjustable except phase.

I guess the system is more like several SISO PID loops that go to a comparator than multiple input. I will edit the title to reflect this.

---------- Post added at 18:51 ---------- Previous post was at 18:45 ----------

It's essentially a digital version of putting all those analog feedback values to amplifiers with set values. The output would then go to a VCO chip.
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My first question is, what makes up the controlled system variation that requires a controller? For start-up, you'll usually want to constrain the manipulated value and ramp the setpoints and/or contraints. For practical purposes, this can be suffcient.

In a more general consideration, one would try to design a controller based on a (most likely nonlinear) state space representation of the system.

P.S.: The term comparators refers to on-off control methods and sounds strange related to PID controllers, I think.

The system varies as the output load is metal. As the power put into it heats it up its properties will change causing the Q curve to shift and change. Some metals, as the go into curie, cause the systems parameters to rise extremely fast. Normally, I would just control power and then cascade it into the phase PID loop and have the voltage and current just trip the system. If they go off I would need to adjust the starting power parameter.

However, this isn't very ideal. I don't want the system to shut off unless it is unstable. The system should be able to respond to the rise in either the voltage and current towards their limits by moving the frequency higher, which in turn lowers the power, which lowers the voltage and current. Also, removing the load from the system will cause the current to rise extremely fast and the power to go way down. As the load is leaving, the system should see the current rising towards its limit and the frequency should go up to compensate before settling on the set point. Right now I can achieve this in cases where the rise is slow but when it's fast it will trip because the current PID loop isn't fast enough to take over the output from the power PID loop. If I raise the k-values to compensate for this I make the steady state more unstable.

---------- Post added at 19:24 ---------- Previous post was at 19:19 ----------

You are correct they are amplifiers not comparators.
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The control strategy isn't quite clear to me. A resonant transducer would be normally controlled by two parameters, frequency (which can be adjusted according to load phase) and power level, set e.g. by a duty cycle or bus voltage and adjusted according to a power setpoint or voltage and current limiting values.

Having only frequency as manipulated value doesn't necessarily achieve controlabilty under all operation conditions. I also assume, that the control system characteristic for voltage, current and input power isn't monotonous, or are you always operating at one side of resonance frequency? I wonder, if a kind of direct control of the switch state would offer a better way to achieve the intended current and voltage limiting.

The system is a parallel resonant LC with a coil on the output. The coil changes with the application. Big coil for bigger loads, small coil for smaller load. The inverters output goes to a transformer and then goes to the output coil producing eddy currents which heat the metal in the coil. The system will have a Q-curve associated with it with the peak power corresponding with resonance. Depending on the matching of all the parameters of the system this Q-curve could be either really steep or really flat (ie: low bandwidth or high bandwidth). Where you're operating on this curve is dependent on the switching frequency of MOSFETS on the inverter board. Therefore, if I control the firing frequency then I control where the system is operating on the curve. The bus voltage is fixed I cannot vary it.

The main condition is to not operate past resonance. It is bad for the parts and going above to below resonance on a curve could potentially blow up the components because of going through the peak on the curve.

The problem I'm having with using limits in the PID loops is that they will saturate if another variable is controlling the system because they want to reach their set points, which depending on the system might not be possible to reach. Then, when there is a change to the system these saturated limits don't respond fast enough to take over from the current limit which is heading towards saturation. For example, removing a load from the coil is going to reduce the power but increase the current. If the PID loop output for the current doesn't go below the power PID loop output before it hits it's limit, the system will trip.

---------- Post added at 20:54 ---------- Previous post was at 20:46 ----------

The power, voltage, and current don't fluctuate unless I'm switching at different frequencies often, which with the proper k values doesn't happen. The system can control on power, voltage, and current very well. The only issue is with big changes in the system that result in a high dv/dt or di/dt.

It looks like this roughly:

Code ASM - [expand]
voltage_pid: pid
port map(
clk        => sys_clk,
reset     => pid_reset,
enable   => voltage_enable,
ref_val   => voltage_set_point,
act_val   => voltage_feedback,
output    => voltage_freq_ref
power_pid: pid
port map(
clk        => sys_clk,
reset     => pid_reset,
enable   => power_enable,
ref_val   => power_set_point,
act_val   => power_feedback,
output    => power_freq_ref
current_pid: pid
port map(
clk        => sys_clk,
reset     => pid_reset,
enable   => current_enable,
ref_val   => current_set_point,
act_val   => current_feedback,
output    => current_freq_ref
phase_pid: pid
port map(
clk        => sys_clk,
reset     => pid_reset,
enable   => phase_enable,
ref_val   => phase_set_point,
act_val   => phase_feedback,
output    => phase_freq_ref
process(sample_clk) begin
        if(rising_edge(sample_clk)) then
                if((voltage_freq_ref < current_freq_ref OR voltage_freq_ref = current_freq_ref)  AND (voltage_freq_ref < phase_freq_ref) AND (voltage_freq_ref < power_freq_ref OR voltage_freq_ref = power_freq_ref)) then
                        duty_cycle_ref <= voltage_freq_ref;
                elsif((current_freq_ref < voltage_freq_ref AND current_freq_ref < phase_freq_ref) AND (current_freq_ref < power_freq_ref OR current_freq_ref = power_freq_ref)) then
                        duty_cycle_ref <= current_freq_ref;
                elsif(power_freq_ref < voltage_freq_ref AND power_freq_ref < current_freq_ref AND power_freq_ref < phase_freq_ref) then
                        duty_cycle_ref <= power_freq_ref;
                        duty_cycle_ref <= phase_freq_ref;
                end if;
        end if;
end process;

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I have used PID on numerous projects and never needed more than one input.
After that it is down to getting the constants right for critical damping.

Saturation (respectively wind-up) shouldn't be an issue with suitable designed digital PIDs. When combining the outputs of multiple controllers, the integrator of the inactive one(s) should be overridden to produce an output value near the actual one. So a seamless switching between active controllers can be achieved.

Besides applying basic concepts of digital controller design, it's mainly a matter of designers craftsmanship, I think. Or go for the big thing, nonlinear state-space design.

I have used PID on numerous projects and never needed more than one input.
If you think of a standard lab power supply with independent voltage and current setpoints, you'll agree, that multiple input (MISO) controllers exist.
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Saturation (respectively wind-up) shouldn't be an issue with suitable designed digital PIDs. When combining the outputs of multiple controllers, the integrator of the inactive one(s) should be overridden to produce an output value near the actual one. So a seamless switching between active controllers can be achieved.

Yes, this is exactly what I was thinking I had to do, which I mentioned in my first post. I just wasn't sure if it was a band-aid fix or a reliable one.

Yes, this is exactly what I was thinking I had to do, which I mentioned in my first post.
I must confess, that I didn't read it thoroughly enough. But I see, that you have been in fact talking about limiting the PID output at a dynamically varied value.

Yes, that's a reasonable way to improve controller performance.

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