I wonder if the following is possible:
Let's say I have 3 module
A - drive out a current to its out_i port
B - drive out a current to its out_i port
C - summarize the input currents from A and B from its in_i port
So the current is connected through 1 net between these 3 modules.
Is it possible to model in system verilog using Real Number Modeling (RNM) such scenario?