multiple array assignment

[RAVI30]

hi every one...
I having a problem in assigning multiple signal in a array ....

Foe example my pro is like this

 if (h>53) then
              a<=y_1;
              b_1 <=((t*Q)+(q(a)));
              p2<=p(b_1);
              p3<= p2 xor DataIn;
              p(b_1) <= p3;
              y_1<=y;

in this example b_1 is the address of the array, and "p" is the array.....

like this multiple calculation of address of the array in one cycle (around 7 to 8 calculation) and assigning some signal to that locations....
plz help me out to solve this problem

 

[TrickyDicky]

I don't understand this problem can you post the full code and any error messages.

 

[RAVI30]

hi...

i need to assign the values(0 or 1)or signal to calculated address location in a array .... like this calculation will be more then one......actually i have getting run time error .... only first signal is assigning to first address after that second, 3rd ,4th all is not assigning to calculated address location with respect to that address....

pro:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity abc is
port( clk : in std_logic;
reset: in std_logic;
DataIn: in std_logic;
code_rate:in std_logic_vector(3 downto 0);
-- sel_NM_sh:in std_logic;
data_out: out std_logic);

end abcd;

architecture arch of abcd is
signal a:integer;
signal w:integer;
signal z:integer;
signal u:integer:=0;
signal p: std_logic_vector(32399 downto 0):=(others=>'0');
signal p2:std_logic;
signal p3:std_logic;
signal p4:std_logic;
signal p5:std_logic;



process(clk,reset,h)
begin
if(clk'event and clk= '1') then
if(reset='1') then
--p<=(others=>'0');
b<=0;
b_1<=0;
a<=0;
p2<='0';
p3<='0';
a<=y_1;

else
if (h>53) then
a<=y_1;
b_1 <=((t*T)+(Q(a)));
if(b_1 < (A) )then
b<=b_1;
else
b<=b_1-(A);
end if;
p2<=p(b);
p3<= p2 xor DataIn;
p(b) <= p3;
y_1<=y;
end if;
end if;
end if;
end process;

process(clk,reset,h)
begin
if(clk'event and clk= '1') then
if(reset='1') then
--p<=(others=>'0');
b<=0;
b_1<=0;
a<=0;
p2<='0';
p3<='0';
a<=y_1;

else
if (h>53) then
a<=y_1;
b_1 <=((t*T)+(Q(a)));
if(b_1 < (A) )then
b<=b_1;
else
b<=b_1-(A);
end if;
p2<=p(b);
p3<= p2 xor DataIn;
p(b) <= p3;
y_1<=y;
end if;
end if;
end if;
end process;

 

[TrickyDicky]

There are problems, here, as many signals are undefined: b, b_1, h, t, y, y_1 and Q.

Do you also realise that VHDL is case insensitive. t*T is just t squared.

 

[FvM]

like this multiple calculation of address of the array in one cycle (around 7 to 8 calculation) and assigning some signal to that locations....

Presumed the problem is about VHDL for synthesis and the array is intended for RAM implementation (strongly suggested with 32k memory bits), then there can't be multiple accesses in a single clock cycle. Even the shown read-modify-write operation will require a dual port RAM and pipelined access. You need to restructure the problem according to available hardware features.

 

[RAVI30]

i have defined all signals ...but after compile and run ... in wave(result) form i m getting problem .... actually in one cycle only i need to assign around 5 different signal to different location in a array ( array p) but i getting only one signal is assigning and other r assigning as "XXXXXX"......
and one more i have used array size of (32000 downto o) ... but it is not synthesizing.....

 

[TrickyDicky]

If you are trying to create a memory, you cannot do it from this code. The XXXX will come from assigning P in 2 processes. You are only allowed to assign a signal in a single process.

I suggest reading the HDL coding style guildline from whichever manufacturer your FPGA is.

 

[RAVI30]

k thank you so much sir.....