Multilevel inverter with 7 mosfets manage with an FPGA

[Easy peasy]

BRAD - BJT's are current driven which makes it easier - up to a point - cannot be used in a high power design

Mosfets need good gate drive - right on the Gate & Source

Almost always local psu's are used ( isolated ) to allow this on multi-level inverters - with opto or Tx signal transmission

the above IR2110 proposal is a bit of a mess.

 

[Jose Enrique Sanchez V.]

I based my design on this post

https://tahmidmc.blogspot.com/2013/01/using-high-low-side-driver-ir2110-with.html

and I connected it as he says with the difference of the ground because I only have two mosfet with gnd.

 

[Easy peasy]

Even though the diagrams are very plain in the above post - you appear to be missing the point completely.... => bang ...!

 

[FvM]

The question is, how can the gate driver problem be fixed? I presume that the 6-switch multilevel scheme works as such, I didn't verify.

In the post #18 schematic, Sa3n and Sa2n can be driven by a half bridge driver. The source of Sa1n and Sa3 also swings to GND/DC- when Sa3n and Sa2n (respectively Sa1n and Sa2n) are closed, they can be driven by two additional high side bootstrap driver (upper halve of IR2110 or e.g. IR2117).

Sa2 and Sa1 source never swings to GND/DC-, their gate drivers can't be supplied by bootstrap method and need isolated DC/DC power supply.

You might however come to the conclusion that bootstrap of Sa1n and Sa3 driver through tow respectively three series switches isn't reliable and they also need isolated power supply. Another possible issue arises, if the inverter is operated at reduced output voltage, e.g. in case of a VFD, and some switches aren't closed in a cycle.