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Multilevel inverter with 7 mosfets manage with an FPGA

Jose Enrique Sanchez V.

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I'm an engineering student from Spain, I've been doing my final assessment about different power electronics, inverters, controlled rectifiers, DC/DC and AC/AC simulated with Matlab Simulink. As the last subject in my project I have decided to do an circuit of a multilevel inverter, which tries to change +12Vdc to a sine wave from +12v t0 -12V, controlled by my FPGA artyA7 and I am having problems to activate the 12 mosfets...
Finally I had had decided to try with an bridge inverter with only 4 mosfets and two driver IR2110 and I achieved that my design worked fine. Now I am working again with the multilevel inverter, with 12 mosfets and 6 IR2110. It has the right shape with 7 levels as you can see in the pic, but the frequency is 3 times the wanted. I design the vhdl code for my fpga to 400hz and as you can see in the simulation it's ok, and when I use an oscilloscope to see every output of the development fpga board it has 400hz... Maybe the oscilloscope the the measure wrong, from wrong time or in the wrong way, because apparently the design is well done???
for your advises
 

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FvM

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Unfortunately, we don't even see the oscilloscope timebase setting in the oscilloscope screenshot. Frequency measurement can be easily fooled by a complex waveform.

I wonder by the way how you manage to drive a multileve inverter with IR2110.
 

Jose Enrique Sanchez V.

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Hello FvM!
I'm not a professional with the oscilloscope, I know that is an useful tool but I haven't learn very much about it… I use the "autoset" button most of the times... If you see in the oscilloscope window it shows "100KS/s 250us", I don´t know if I have to change some of parameters to measure fine this wave, I always use the configuration by default. It is strange because the frequency obtained is 3 times the 400Hz wanted, it is faster than the reality, and if some of components work badly the frequency should be slower... for this reason I think that maybe the mistake is in the way of the measurement of the oscilloscope...
I try with several designs to achieve shoot the mosfets in this kind of inverter, directly from the development board to the logic level mosfet IRL530, using a driver BC548, with the IR2110 and the optocoupler vishay VOH1016AD-V , but finnaly I found this design from Tahmid on
and the bridge design works fine.Now I am trying again with the multilevel inverter and I haven't much help from the university and I have to lock on several books and internet...
Thanks for your answer and help :)
 

FvM

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O.k. 250 us/div, if I see right, the screen has 12 divisions and the wave period is 10 divisions or 2.5 ms, thus correct 400 Hz.

As for the IR2110 in multilevel circuit question, we would need to see the complete schematic.
 

BradtheRad

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Looking at your timing diagram, the upper five waveforms are all right, but I believe the bottom five are upside down.
Simulacion_FPGA_.PNG

My simulation is 5-level diode-clamped. (Concepts are similar to yours.) Notice the pattern of 'On' times. Top and bottom switches are the shortest. Middle switches are the longest.

Also notice the frequency at the load, resulting from control signals applied by the window comparator network.

5-level diode-clamped 5 opamps 3 inv-gates 8 ana-switches load gets 50VAC sine-like.png
 

Easy peasy

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1 / ( 14 x 250uS ) = 285.71 Hz ...
--- Updated ---

for 50Hz each of the 14 steps needs to be 1.428mS, for 400Hz each of the 14 steps needs to be 178.56uS long
 

Jose Enrique Sanchez V.

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O.k. 250 us/div, if I see right, the screen has 12 divisions and the wave period is 10 divisions or 2.5 ms, thus correct 400 Hz.

As for the IR2110 in multilevel circuit question, we would need to see the complete schematic.
Ok, ok you are right FvM observing the divisions it's true that the sum is 2.5ms, the 400Hz desired.
About the IR2110, I connected it following the design of Tahmid's blog for H bridge, but instead of 4 mosfets, I have 12. I used 3 ir2110 in each leg, each ir2110 with high and low mosfet. If you see the image of my Simulink design in the first post, I use the high output(7) and the low output(1) of the first ir2110 to feed the mosfet Sa1 and Sa2 respectively. I tried in different ways, even with the datasheet of infineon but the tahmid's design was the best option. I think that this design works fine.
I am really enjoying with this practical part of my design, I like very much power electronics and FPGA.
 

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Jose Enrique Sanchez V.

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1 / ( 14 x 250uS ) = 285.71 Hz ...
--- Updated ---

for 50Hz each of the 14 steps needs to be 1.428mS, for 400Hz each of the 14 steps needs to be 178.56uS long
Hi easy peasy!
Fvm is right, there are 10 divs, then the frequency is 400Hz. Thanks for your point of view, I am here to learn, and I want to learn a lot about this :)
 

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FvM

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If I read the breadboard wiring correctly, all IR2110 are connected to a common ground and power supply. But 4 of 6 devices don't drive a ground connected low side transistor, which is the prerequisite for correct operation of the driver.
 

Jose Enrique Sanchez V.

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hello @BradtheRad , I am not a professional about inverters, I was researching many time about different designs and I decided to use this circuit. I use the selected harmonics elimination way to decide how I should to active each mosfet, I active each mosfet following my diagram, which I have founded in some course or book. I don't know if my topology is an real option, I read a lot about it but I have not other point of view, thanks :) I share the pic of my diagram and a simulation of my first design.
 

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Easy peasy

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A ha, FvM is right you can only use the top half of the 2110 to drive devices that are not source = gnd, and you must allow for bootstrap charging if they are not fed by individual isolated gate drive supplies
 

Jose Enrique Sanchez V.

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If I read the breadboard wiring correctly, all IR2110 are connected to a common ground and power supply. But 4 of 6 devices don't drive a ground connected low side transistor, which is the prerequisite for correct operation of the driver.
Yes, I observed it and I tried to connect the low output between the gate of the low mosfet and the ground thru the resistance , but in this way I only obtain a wave with 3 levels but when I try with from gate of the low mosfet to the drain of the next mosfet, apparently It works fine, as we can see on the oscilloscope. I am a begginer on this, but I think that it works good
 

Jose Enrique Sanchez V.

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A ha, FvM is right you can only use the top half of the 2110 to drive devices that are not source = gnd, and you must allow for bootstrap charging if they are not fed by individual isolated gate drive supplies
Yes, I understand it, but it apparently works fine, maybe with 12 ir2110 it works in different way... I am not sure about the application of this design in a real situation but in a simulation field it looks apparently fine. My teacher don't know a lot about it and I have looking for information on different places. I really appreciate your opinions, thanks very much. I want to learn on this field.
 

FvM

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You didn't yet show a complete schematic of your circuit.
 

d123

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Hi,

Just out of curiosity, are all the ground rails on the breadboard identical in value when measured from input ground and from ground rail to ground rail? I only ask as I had an issue with a breadboard the other day where one ground rail measured 1.8mV and another a horrifying 6mV in comparison to the input ground and to the other grounds.
 

mtwieg

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I advise that you use isolated supplies for your gate drivers. At least as a starting point.

While it is possible in principle to use bootstrapping drivers like the IR2110 for driving multilevel inverters, doing so requires that you occasionally recharge every bootstrap capacitor. Doing this requires that you simultaneously turn on every FET except the two connected to your positive supply rail. This isn't a switch state which you would normally use when synthesizing a sine wave output, so you will need to force this state to occur every so often (depending on the size of the bootstrap caps and their loads).
 

Jose Enrique Sanchez V.

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You didn't yet show a complete schematic of your circuit.
Hi, I did the schematic yesterday after work, I have no many time to do my project, sorry for my delay..
I spoke with the support of infineon and a someone told me that I can connect it in this way, and then I did it. I only need to have an sine wave because this is only a portion of my project, and I haven't help of my teacher or anyone in my university then it's a little bit complicated for me. I am a conscientious person who want to do things well done, but I have only this month to finish it, and with my working journey it is complicated. I think that with this schematic maybe it is not perfect but works. If I would have more time I would have in a better way and I have to try to do an buck converter with my fpga...
I really appreciate your words and opinions, thanks at all for your advice
 

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Easy peasy

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Unfortunately - unlikely to work - very likely to blow up the 2110's though ...
--- Updated ---

pins 11,12 need to go to the local lower device source - exactly as it is done on the very lower ones ....
--- Updated ---

also - there is no way for the upper devices boot-strap caps to charge ...
 

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See if this idea makes it easier to apply gating pulses...
Use P-devices for the upper half, rather than N-devices. Their bias current has a more definite path since it comes through the positive supply rail. (Notice that a high side N-device creates more trouble to bias it since its bias current does not necessarily have a definite path through the load.)

That made it easier to get a 3-level converter to work (in my own simulation, that is).

3-level diode-clamped 2 PNP 2 NPN 2 caps load is RL.png

I am not sure about the application of this design in a real situation
The diode-clamped topology is most useful when the load is inductive. The switches are shut off in sequence thus the diodes function as a snubbing network.
 

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