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multilevel inverter current zero but voltage shows

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Mar 12, 2014
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i tried to implement a multilevel inverter. i done already in matlab which shows what i want. during the hardware implementation the output voltage shows the same result as in matlab if load is zero. when i connect a load the output voltage becomes zero no current flows through it.why this problem occurs.
the sources are 3 nos of 12V battery which are in good condition.


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filter inductor and capacitor are removed from the circuit.

The schematic in post #1 doesn't make much sense without telling what's connected here and there, and what are the controlling waveforms. The schematic also doesn't seem to implement a standard multilevel scheme.

Try to ask a complete question!

this type inverter is a new concept with a new PWM method. The results are very good in matlab simulation,now the problem comes on the hardware implementation.

In hardware the voltage shape is same as the simulation result. but not building the current.

What to say without any details? Either the simulation is wrong or the real circuit is different from the simulation setup, or it has properties not covered by the simulation.

Switches z1,z2,z5,z6 are act as H bridge circuit.
For attaining Multilevel other 4 switches are used.for achieving first level Z8& z4 are ON.For second level z8 & z3 ON. For third level Z3&Z7 are ON.
This is my design consideration.

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filter inductor and capacitor are removed from the circuit.

please attach your simulation or experimental waveforms of current and voltage.
It has be noted that this is not a new configuration. It just a hybrid implementation of a 2-level H-bridge inverter and a modular multilevel inverter as it can be conceived form schematic.

P.S please delete the filter; connect the output to a resistor, and report requested waveform.

Of course you need a break or dead time of around 0.5us and the bridge source will rise with higher frequency due to duty cycle of open circuit. Reff= RdsOn (total)./D
You have 4 potential pairs for shootthru failure which demand deadtime control on the gate.

% Load Regulation of output will be Rsource/Rload

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