lucianom
Newbie level 3
I try to simulate in LTSpice an NMOS transistor with a 3 finger layout. That is, the Wfinal = Winitial / 3 and CSB = 2CSB / 3.
How should I simulate this in LTSpice? does the parameter "parallel devices M" already do that? or how should I use the values "source area AD" and "source perimeter SP"?
thank in advance.
Luciano Martinez
How should I simulate this in LTSpice? does the parameter "parallel devices M" already do that? or how should I use the values "source area AD" and "source perimeter SP"?
thank in advance.
Luciano Martinez