specifying clock to clock false paths
Hi kil:
Yes it slows down the STA timer. Every timing exception is an additional rule that must be added to the basic STA algorithm. And each one requires CPU time to check which slows down the tool. A handful more or less doesn't make any difference, but long complex lists of timing exceptions are a drag for most tools. I cannot vouch that this is true for every last tool, but it is true for many EDA tools, including P&R.
Keep in mind that you must absolutely specify all significant timing exceptions or the optimization tool will focus on trying to fix spurious timing problems. But it is not desirable nor possible to list all the exceptions exhaustively.
If a timing exception, for example, a false path does not cause any timing violations then we don't care if the P&R tool does some minor bit of unecessary optimization to optimize this false path.
So you only need to list those exceptions that would otherwise rise to near the top of the critical path list. Unfortunately these can usually only be identified through trial and error.