[SOLVED] Multicycle path synthesis

[stevenv07]

Hello everyone,

My design has many clock domains. For simplicity, let's take 2 clock domains. One is master clock clk, and another one is generated clock clk_div_40 from the master.

clk_div_40 -> FF1 -> FF2 (clk)

I set multicycle path as follows

set_multicycle_path 40 -setup -from clk_div_40 -to clk -end

When design compiler generates sdc file, it changes 40 cycles to 39 cycles. I dont know why it change my setting. Could you explain me this?

Thank you so much.
Steve.

 

[ThisIsNotSam]

do a report_clocks and check if it says 39 there. you might be misinterpreting the timing analysis.