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Multicycle CPU MIPS datapath design

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panda1234

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Hi,
suppose we want to create data path of multicycle MIPS processor.our clock frequency is 400MHz and we want to execute every instruction in minimum time.(delay of Controllers and multiplexers is zero)

Instructions to be Implemented: addu, addui, and, andi, beq, bne, lw, sw
Memory:
Address to Read-Data propagation delay: 9 ns
Write to Read/Write access time: 4 ns
Write-Data setup time: 0.1 ns
Write is controlled by positive edge of clock
Register File:
Read-Register to Read-Data propagation delay: 2 ns
Write-Register & Write-Data setup time: 0.1 ns
Registers:
Clock to Q delay: 0.1 ns
Input setup time: 0.1 ns
ALU:
Inputs to Outputs propagation delay: 2 ns

now my problem here.in below you will see multicycle processor's data path what's difference between it's data path and this problem?

MUCPU.png
 

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