Multiclock design(Argent)

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ssudhasa

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Hi, I have a question.

CLKA = 2 × CLKB

Signal in CLKA domain is active for 2 CLKA cycle.

At clock domain crossing we have used 2 bit synthronizer,
At synthronizer output, how many CLKB cycles it will have . ??

options:
(1) 1
(2) 2
(3) 3

And Also , for this MCD scenario, 2 bit synthronizer is sufficient?

Thanks in Anticipation!!
 

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