#define EMAC1_BASEADDR 0x7C400000
#define EMAC2_BASEADDR 0x7C500000
#define FAULTINHIBIT_OFFSET_REG 0x410
#define MAC_FAULT_BITS 0x30000000
#define FI_BIT 0x08000000
#define FI_BIT_MASK 0xF7FFFFFF
void toggle_EMAC_fault_inhibit(void)
{
int reconciliation_reg = 0;
reconciliation_reg = Xil_In32(EMAC1_BASEADDR + FAULTINHIBIT_OFFSET_REG);
if (reconciliation_reg & FI_BIT){
FI = 0;
xil_printf("\r\nFault Inhibit: Disabled\r\n");
Xil_Out32(EMAC1_BASEADDR + FAULTINHIBIT_OFFSET_REG, reconciliation_reg & FI_BIT_MASK);
Xil_Out32(EMAC2_BASEADDR + FAULTINHIBIT_OFFSET_REG, reconciliation_reg & FI_BIT_MASK);
}
else{
FI = 1;
xil_printf("\r\nFault Inhibit: Enabled\r\n");
Xil_Out32(EMAC1_BASEADDR + FAULTINHIBIT_OFFSET_REG, reconciliation_reg | FI_BIT);
Xil_Out32(EMAC2_BASEADDR + FAULTINHIBIT_OFFSET_REG, reconciliation_reg | FI_BIT);
}
}
void Enable_EMAC_fault_inhibit(void)
{
do{
Xil_Out32(EMAC1_BASEADDR + FAULTINHIBIT_OFFSET_REG, Xil_In32(EMAC1_BASEADDR + FAULTINHIBIT_OFFSET_REG) | FI_BIT);
Xil_Out32(EMAC2_BASEADDR + FAULTINHIBIT_OFFSET_REG, Xil_In32(EMAC2_BASEADDR + FAULTINHIBIT_OFFSET_REG) | FI_BIT);
} while (((Xil_In32(EMAC1_BASEADDR + FAULTINHIBIT_OFFSET_REG) & Xil_In32(EMAC2_BASEADDR + FAULTINHIBIT_OFFSET_REG))&FI_BIT_MASK) == 0);
}