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Multibank handling in DDR SDRAM Controller

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cafukarfoo

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Hi everyone,

Can anyone explain in details for statement below.

"multibank architecture allow for concurrent operation to enable to hide row precharge/activation time"

I wonder how can i write concurrently because DDR SDRAM only have single DQS, DQ and control signal such as we, ras, and cas.

Thanks in advance for your help.
 

I would say it is refering to the Bank feature. If you are accessing another bank you need not to close the page (ie. precharge). So it is nothing special
 

It means that you can fire a command on say bank 1 and expect the data 3 cycles later. the preceding 2 cycles can be used to fire command on other bank .and expect their output at cycles 4,5 and so on
 

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